Ingaas epi structure and wet etch process for enabling III-v GAA in art trench

Patent metadata

Field	Value
Publication number	US-11631737-B2
Application number	US-201415529481-A
Country	US
Kind code	B2
Filing date	Dec 24, 2014
Priority date	Dec 24, 2014
Publication date	Apr 18, 2023
Grant date	Apr 18, 2023

Abstract

Embodiments of the invention include nanowire and nanoribbon transistors and methods of forming such transistors. According to an embodiment, a method for forming a microelectronic device may include forming a multi-layer stack within a trench formed in a shallow trench isolation (STI) layer. The multi-layer stack may comprise at least a channel layer, a release layer formed below the channel layer, and a buffer layer formed below the channel layer. The STI layer may be recessed so that a top surface of the STI layer is below a top surface of the release layer. The exposed release layer from below the channel layer by selectively etching away the release layer relative to the channel layer.

First claim

What is claimed is:

1. A method for forming a microelectronic device, comprising:
forming a multi-layer stack within a trench formed in a shallow trench isolation (STI) layer, wherein growth of the multi-layer stack is confined by the STI layer, wherein the multi-layer stack comprises at least a channel layer, a release layer formed below the channel layer, and a buffer layer formed below the channel layer, wherein the buffer layer is formed over a substrate layer, wherein the substrate layer has a notched surface, wherein the notched surface has an uppermost point in contact with a vertical sidewall of the STI layer;
recessing the STI layer so that a top surface of the STI layer is below a top surface of the release layer;
forming a sacrificial gate electrode over a portion of the multi-layer stack and the STI layer subsequent to recessing the STI layer below the channel layer and below a top surface of the release layer;
forming sidewall spacers along sidewalls of the sacrificial gate electrode;
removing portions of the multi-layer stack that are not covered by the sacrificial gate electrode; and
forming replacement source/drain regions where the removed portions of the multi-layer stack were formed, the replacement source/drain regions in lateral contact with the sidewall spacers at a location over the multi-layer stack; and
removing the release layer with an etching process that selectively removes the release layer relative to the channel layer.

2. The method of claim 1 , wherein the STI layer is formed over the substrate layer, and wherein the multi-layer stack is epitaxially grown over the substrate layer.

3. The method of claim 2 , wherein the buffer layer, the release layer and the channel layer are each a III-V semiconductor material and the substrate layer is a silicon layer.

4. The method of claim 3 , wherein the buffer layer is GaAs, poly-GaAs, or InP, the release layer is InP, and the channel layer is InGaAs.

5. The method of claim 4 , wherein the etching process that selectively removes the release layer relative to the channel layer is a wet-etching process that includes HCl and H 2 SO 4 .

6. The method of claim 1 , wherein the trench has an aspect ratio that is 2:1 or greater prior to being recessed.

7. The method of claim 6 , wherein the buffer layer accounts for at least a quarter of the thickness of the multi-layer stack.

8. The method of claim 1 , wherein the release layer has a thickness to width ratio that is 3:2 or greater.

9. The method of claim 1 , wherein the channel layer is a nanowire channel layer or a nanoribbon channel layer.

10. The method of claim 1 , further comprising:
forming an interlayer dielectric (ILD) layer over the portions of the STI layer and the multi-layer stack that are not covered by the sacrificial gate electrode or the sidewall spacers.

11. The method of claim 10 , further comprising:
removing the sacrificial gate electrode prior to removing the release layer;
forming a bottom gate isolation layer over an exposed surface of the buffer layer that is between the sidewall spacers;
forming a gate dielectric layer over the exposed surfaces of the channel layer that are between the sidewall spacers; and
forming a gate electrode around the portion of the channel layer that is between the sidewall spacers.

12. The method of claim 1 , wherein the multi-layer stack further comprises a second release layer formed above a top surface of the channel layer, and a second channel layer formed above a top surface of the second release layer.

13. The method of claim 12 , wherein the etching process that selectively removes the release layer relative to the channel layer also selectively removes the second release layer relative to the second channel layer.

14. A method for forming a microelectronic device, comprising:
forming a multi-layer stack within a trench formed in a shallow trench isolation (STI) layer, wherein growth of the multi-layer stack is confined by the STI layer, wherein the multi-layer stack comprises at least a channel layer, a release layer formed below the channel layer, and a buffer layer formed below the channel layer, wherein the buffer layer is GaAs or poly-GaAs, the release layer is InP, and the channel layer is InGaAs, and wherein the release layer has a thickness to width ratio that is 3:2 or greater, and wherein the buffer layer is formed over a substrate layer, wherein the substrate layer has a notched surface, wherein the notched surface has an uppermost point in contact with a vertical sidewall of the STI layer;
recessing the STI layer so that a top surface of the STI layer is below a top surface of the release layer;
forming a sacrificial gate electrode over a portion of the multi-layer stack and the STI layer;
forming sidewall spacers along sidewalls of the sacrificial gate electrode;

removing portions of the multi-layer stack that are not covered by the sacrificial gate electrode;
forming replacement source/drain regions where the removed portions of the multi-layer stack were formed, the replacement source/drain regions in lateral contact with the sidewall spacers at a location over the multi-layer stack;
forming an interlayer dielectric (ILD) layer over the portions of the STI layer and
the multi-layer stack that are not covered by the sacrificial gate electrode or the sidewall spacers;
removing the sacrificial gate electrode;
forming a bottom gate isolation layer over an exposed surface of the buffer layer that is between the sidewall spacers;
removing the release layer with an etching process that selectively removes the release layer relative to the channel layer;
forming a gate dielectric layer over the exposed surfaces of the channel layer that are between the sidewall spacers; and
forming a gate electrode around the portion of the channel layer that is between the sidewall spacers.

15. The method of claim 14 , wherein the channel layer is a nanowire channel layer or a nanoribbon channel layer.

16. The method of claim 14 , wherein the trench has an aspect ratio that is 2:1 or greater prior to being recessed, and wherein the buffer layer accounts for at least a quarter of the thickness of the multi-layer stack.

Assignees

• Intel Corp

Inventors

• Gardner Sanaz K
• Rachmady Willy
• Metz Matthew V
• Dewey Gilbert
• Kavalieros Jack T
• Mohapatra Chandra S
• Murthy Anand S
• Rahhal-Orabi Nadia M
• Zelick Nancy M
• Ghani Tahir

Classifications

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D62/82 Primary

  Heterojunctions · CPC title

• H10D30/6215 Primary

  having multiple independently-addressable gate electrodes · CPC title