Scalable interrupts

Patent metadata

Field	Value
Publication number	US-11630789-B2
Application number	US-202117246311-A
Country	US
Kind code	B2
Filing date	Apr 30, 2021
Priority date	Sep 11, 2020
Publication date	Apr 18, 2023
Grant date	Apr 18, 2023

Abstract

An interrupt delivery mechanism for a system includes and interrupt controller and a plurality of cluster interrupt controllers coupled to respective pluralities of processors in an embodiment. The interrupt controller may serially transmit an interrupt request to respective cluster interrupt controllers, which may acknowledge (Ack) or non-acknowledge (Nack) the interrupt based on attempting to deliver the interrupt to processors to which the cluster interrupt controller is coupled. In a soft iteration, the cluster interrupt controller may attempt to deliver the interrupt to processors that are powered on, without attempting to power on processors that are powered off. If the soft iteration does not result in an Ack response from one of the plurality of cluster interrupt controllers, a hard iteration may be performed in which the powered-off processors may be powered on.

First claim

What is claimed is:

1. A system comprising:
a plurality of cluster interrupt controllers, wherein a respective cluster interrupt controller of the plurality of cluster interrupt controllers is associated with a respective processor cluster of a plurality of processor clusters, and wherein a given processor cluster of the plurality of processor clusters comprises a plurality of processors; and
an interrupt controller coupled to the plurality of cluster interrupt controllers, wherein the interrupt controller is configured to receive an interrupt from a first interrupt source and is configured, based on the interrupt, to:
perform a first iteration over the plurality of cluster interrupt controllers to attempt to deliver the interrupt;
based on non-acknowledge (Nack) responses from the plurality of cluster interrupt controllers in the first iteration, perform a second iteration over the plurality of cluster interrupt controllers;
wherein a given cluster interrupt controller of the plurality of cluster interrupt controllers, in the first iteration, is configured to attempt to deliver the interrupt to a subset of the plurality of processors in the respective processor cluster that are powered on without attempting to deliver the interrupt to ones of the respective plurality of processors in the respective processor cluster that are not included in the subset; and
wherein the given cluster interrupt controller, in the second iteration, is configured to power on the ones of the plurality of processors that are powered off and attempt to deliver the interrupt to the plurality of processors.

2. The system as recited in claim 1 wherein, during the attempt to deliver the interrupt over the plurality of cluster interrupt controllers:
the interrupt controller is configured to assert a first interrupt request to a first cluster interrupt controller of the plurality of cluster interrupt controllers; and
based on the Nack response from the first cluster interrupt controller, the interrupt controller is configured to assert a second interrupt request to a second cluster interrupt controller of the plurality of cluster interrupt controllers.

3. The system as recited in claim 2 wherein, during the attempt to deliver the interrupt over the plurality of cluster interrupt controllers:
based on a second Nack response from the second cluster interrupt controller, the interrupt controller is configured to assert a third interrupt request to a third cluster interrupt controller of the plurality of cluster interrupt controllers.

4. The system as recited in claim 2 wherein, during the attempt to deliver the interrupt over the plurality of cluster interrupt controllers:
based on an acknowledge (Ack) response from the second cluster interrupt controller and a lack of additional pending interrupts, the interrupt controller is configured to terminate the attempt.

5. The system as recited in claim 1 wherein, during the attempt to deliver the interrupt over the plurality of cluster interrupt controllers:
the interrupt controller is configured to assert an interrupt request to a first cluster interrupt controller of the plurality of cluster interrupt controllers; and
based on an acknowledge (Ack) response from the first cluster interrupt controller and a lack of additional pending interrupts, the interrupt controller is configured to terminate the attempt.

6. The system as recited in claim 1 wherein, during the attempt to deliver the interrupt over the plurality of cluster interrupt controllers:
the interrupt controller is configured to serially assert interrupt requests to one or more cluster interrupt controllers of the plurality of cluster interrupt controllers, terminated by an acknowledge (Ack) response from a first cluster interrupt controller of the one or more cluster interrupt controllers.

7. The system as recited in claim 6 wherein the interrupt controller is configured to serially assert in a programmable order.

8. The system as recited in claim 6 wherein the interrupt controller is configured to serially assert the interrupt request based on the first interrupt source, wherein a second interrupt from a second interrupt source results in a different order of the serial assertion.

9. The system as recited in claim 1 wherein, during the attempt to deliver the interrupt over the plurality of cluster interrupt controllers:
the interrupt controller is configured to assert an interrupt request to a first cluster interrupt controller of the plurality of cluster interrupt controllers; and
the first cluster interrupt controller is configured to serially assert processor interrupt requests to the plurality of processors in the respective processor cluster based on the interrupt request to the first cluster interrupt controller.

10. The system as recited in claim 9 wherein the first cluster interrupt controller is configured to terminate serial assertion based on an acknowledge (Ack) response from a first processor of the plurality of processors.

11. The system as recited in claim 10 wherein the first cluster interrupt controller is configured to transmit the Ack response to the interrupt controller based on the Ack response from the first processor.

12. The system as recited in claim 9 wherein the first cluster interrupt controller is configured to provide the Nack response to the interrupt controller based on Nack responses from the plurality of processors in the respective cluster during the serial assertion of processor interrupts.

13. The system as recited in claim 1 wherein the interrupt controller is included on a first integrated circuit on a first semiconductor substrate that includes a first subset of the plurality of cluster interrupt controllers, and wherein a second subset of the plurality of cluster interrupt controllers are implemented on a second integrated circuit on second, separate semiconductor substrate, and wherein the interrupt controller is configured to serially assert interrupt requests to the first subset prior to attempting to deliver to the second subset.

14. The system as recited in claim 13 wherein the second integrated circuit includes a second interrupt controller, and wherein the interrupt controller is configured to communicate the interrupt request to the second interrupt controller responsive to the first subset refusing the interrupt, and wherein the second interrupt controller is configured to attempt to deliver the interrupt to the second subset.

15. A processor comprising:
a reorder buffer configured to track a plurality of instruction operations corresponding to instructions fetched by the processor and not retired by the processor;
a load/store unit configured to execute load/store operations; and
a control circuit coupled to the reorder buffer and the load/store unit, wherein the control circuit is configured to generate an acknowledge (Ack) response to an interrupt request received by the processor based on a determination that the reorder buffer will retire instruction operations to an interruptible point and the load/store unit will complete load/store operations to the interruptible point within a specified period of time, and wherein the control circuit is configured to generate a non-acknowledge (Nack) response to the interrupt request based on a determination that at least one of the reorder buffer and the load/store unit will not reach the interruptible point within the specified period of time.

16. The processor as recited in claim 15 wherein the determination is the Nack response based on the reorder buffer having at least one instruction operation th

Assignees

• Apple Inc

Inventors

• Gonion Jeffrey E
• Tucker Charles E
• Kuzi Tal
• Russo Richard F
• Agarwal Mridul
• Tsay Christopher M
• Levinsky Gideon N
• Wen Shih-Chieh
• Zimet Lior

Classifications

• G06F13/24 Primary

  using interrupt (G06F13/32 takes precedence) · CPC title

• G06F1/26

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title

• G06F9/5027

  the resource being a machine, e.g. CPUs, Servers, Terminals · CPC title

• G06F9/4812 Primary

  by interrupt, e.g. masked · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title