Reconfigurable stand alone distributed system motor controllers

Patent metadata

Field	Value
Publication number	US-11630748-B2
Application number	US-201916365931-A
Country	US
Kind code	B2
Filing date	Mar 27, 2019
Priority date	Mar 27, 2019
Publication date	Apr 18, 2023
Grant date	Apr 18, 2023

Abstract

Methods and systems for operating internal systems of a vehicle are provided. Aspects include providing a field programmable gate array (FPGA), the FPGA including a communication channel port, wherein the communication channel port is operable to connect to one or more systems through a communication channel, and wherein the FPGA is configured to operate in one or more control modes, receiving a communication channel input to the communication channel port of the FPGA, based at least in part on the communication channel input, determining a control mode from the one or more control modes, and operating the FPGA in the control mode, wherein the control mode is associated with one system of the one or more systems.

First claim

What is claimed is:

1. A method comprising:
providing a field programmable gate array (FPGA), the FPGA including a communication channel port, wherein the communication channel port that includes a plurality of pin inputs operable to connect to one or more systems having a pin connectors, and
wherein the FPGA is configured to operate in one or more control;
receiving a communication channel input from a first system of the one or more system via the pin connectors at the plurality of pin inputs of the communication channel port of the FPGA;
based at least in part on the communication channel input, determining a first control mode from the one or more control modes; and
operating the FPGA in the first control mode, wherein the first control mode is associated with one system of the one or more systems;
wherein determining the first control mode from the one or more control modes comprises analyzing a configuration of the pin connectors, wherein the configuration is based on a presence or absence of pin connectors of the first system;
mapping the configuration of the pin connectors to a binary number; and
comparing the binary number to a look-up table stored in a memory associated with the FPGA to determine the first control mode.

2. The method of claim 1 further comprising:
receiving a second communication channel input to the communication channel port of the FPGA;
based at least in part on the communication channel input, determining a second control mode from the one or more control modes; and
operating the FPGA in the second control mode.

3. The method of claim 1 , wherein the one or more control modes comprise a plurality of operation parameters for the one or more systems.

4. The method of claim 3 , wherein the plurality of operation parameters comprise gain, shutdown control, and speed settings for the one or more systems.

5. The method of claim 1 , wherein the one or more control modes comprise an FPGA designation.

6. The method of claim 5 , wherein the FPGA designation comprises a primary designation, a secondary designation, and a tertiary designation.

7. The method of claim 1 , wherein the one system of the one or more systems comprises an internal system of a vehicle.

8. The method of claim 7 , wherein the vehicle is a spacecraft and the internal system within the vehicle is hardened against a radiation environment.

9. A system comprising:
a field programmable gate array (FPGA) including a communication channel port, the communication channel port operable to connect to one or more systems through a communication channel, wherein the FPGA is configured to operate in one or more control modes; and
wherein the FPGA is configured to:
receive, at the communication channel port, a communication channel input;

determine a first control mode from the one or more control modes based at least in part on the communication channel input; and
operate in the first control mode, wherein the control mode is associated with one system of the one or more systems .
wherein the communication channel port comprises a plurality of pin inputs;
wherein the communication channel input comprises a plurality of pin connectors;
wherein determining the first control mode from the one or more control modes comprises analyzing a configuration of the plurality of pin connectors, wherein the configuration is based on a presence or absence of the plurality of pin connectors;
mapping the configuration of the plurality of pin connectors to a binary number; and
comparing the binary number to a look-up table stored in a memory associated with the FPGA to determine the first control mode.

10. The system of claim 9 , wherein the FPGA is further configured to:
receive a second communication channel input to the communication channel port of the FPGA;
determine a second control mode from the one or more control modes based at least in part on the second communication channel input; and
operate in the second control mode.

11. The system of claim 9 , wherein the one or more control modes comprise a plurality of operation parameters for the one or more systems.

12. The system of claim 11 , wherein the plurality of operation parameters comprise gain, shutdown control, and speed settings for the one or more systems.

13. The system of claim 9 , wherein the one or more control modes comprise an FPGA designation.

14. The system of claim 13 , wherein the FPGA designation comprises a primary designation, a secondary designation, and a tertiary designation.

Assignees

• Hamilton Sundstrand Corp

Inventors

• Wichowski Robert P
• Roberts Timothy A
• Sears Patrick J

Classifications

• H10W42/20

  protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons · CPC title

• G05B7/02

  electric · CPC title

• G06F16/9017

  using directory or table look-up (use of a directory or look-up table in file systems G06F16/13) · CPC title

• G06F15/7867

  with reconfigurable architecture · CPC title

• G05B2219/21109

  Field programmable gate array, fpga as I-O module · CPC title