Method and system for decoding data based on association of first memory location and second memory location

Patent metadata

Field	Value
Publication number	US-11630722-B2
Application number	US-202117503198-A
Country	US
Kind code	B2
Filing date	Oct 15, 2021
Priority date	Mar 12, 2013
Publication date	Apr 18, 2023
Grant date	Apr 18, 2023

Abstract

An error management system for a data storage device can generate soft-decision log-likelihood ratios (LLRs) using multiple reads of memory locations. Bit patterns provided by multiple reads of reference memory locations can be counted and used to generate probability data that is used to generate possible LLR values for decoding target pages. Possible LLR values are stored in one or more look-up tables.

First claim

What is claimed is:

1. A data storage system, comprising:
memory having one or more first memory locations and one or more second memory locations; and
one or more controllers configured to cause:
receiving first data from the one or more first memory locations;
performing a plurality of reads for one or more memory cells at the one or more first memory locations;
obtaining read values based on the plurality of reads;
determining log likelihood ratios (LLRs) based on the first data and the read values;
selecting, for the one or more second memory locations, one or more LLRs from the LLRs, based on an association between the one or more second memory locations and the one or more first memory locations; and
decoding second data from the one or more second memory locations using the selected one or more LLRs.

2. The data storage system of claim 1 , wherein the one or more controllers are configured to cause determining that the one or more second memory locations are associated with the one or more first memory locations.

3. The data storage system of claim 2 , wherein:
determining that the one or more second memory locations are associated with the one or more first memory locations comprises determining that the one or more second memory locations are located in physical proximity to the one or more first memory locations; and
the physical proximity is within a threshold proximity value.

4. The data storage system of claim 1 , wherein the association between the one or more second memory locations and the one or more first memory locations is a predetermined association between the one or more second memory locations and the one or more first memory locations.

5. The data storage system of claim 1 , wherein the one or more controllers are configured to cause:
obtaining one or more first data retention characteristics of the one or more first memory locations and one or more second data retention characteristics of the one or more second memory locations,
wherein selecting the one or more LLRs comprises selecting the one or more LLRs based on the one or more first data retention characteristics and the one or more second data retention characteristics.

6. The data storage system of claim 1 , wherein the one or more controllers are configured to cause:
determining whether data in one or more third memory locations is successfully decoded using a first read voltage; and
when the one or more third memory locations is not successfully decoded using the first read voltage:
decoding data in one or more fourth memory locations using the first read voltage; and
when the data in the one or more fourth memory locations is successfully decoded using the first read voltage, identifying the data in the one or more fourth memory locations as the first data.

7. The data storage system of claim 6 , wherein the one or more controllers are configured to cause: when the one or more third memory locations is successfully decoded using the first read voltage, identifying the data in the one or more third memory locations as the first data.

8. The data storage system of claim 1 , wherein the read values are correlated with the first data.

9. The data storage system of claim 1 , wherein the one or more controllers are configured to cause: placing the LLRs into a data structure associated with the one or more first memory locations.

10. The data storage system of claim 1 , wherein the one or more controllers are configured to cause: periodically updating at least one LLR of the LLRs, based on one or more decode operations performed on data stored in the one or more second memory locations.

11. A method for a data storage system, the method comprising:
receiving first data from one or more first memory locations;
performing a plurality of reads for one or more memory cells at the one or more first memory locations;
obtaining read values based on the plurality of reads;
determining log likelihood ratios (LLRs) based on the first data and the read values;
determining, for one or more second memory locations, one or more LLRs from the LLRs, based on an association between the one or more second memory locations and the one or more first memory locations; and
decoding second data from the one or more second memory locations using the determined one or more LLRs.

12. The method of claim 11 , comprising: determining that the one or more second memory locations are associated with the one or more first memory locations.

13. The method of claim 12 , wherein:
determining that the one or more second memory locations are associated with the one or more first memory locations comprises determining that the one or more second memory locations are located in physical proximity to the one or more first memory locations; and
the physical proximity is within a threshold proximity value.

14. The method of claim 11 , wherein the association between the one or more second memory locations and the one or more first memory locations is a predetermined association between the one or more second memory locations and the one or more first memory locations.

15. The method of claim 11 , comprising:
obtaining one or more first data retention characteristics of the one or more first memory locations and one or more second data retention characteristics of the one or more second memory locations,
wherein determining the one or more LLRs comprises determining the one or more LLRs based on the one or more first data retention characteristics and the one or more second data retention characteristics.

16. The method of claim 11 , comprising:
determining whether data in one or more third memory locations is successfully decoded using a first read voltage; and
when the one or more third memory locations is not successfully decoded using the first read voltage:
decoding data in one or more fourth memory locations using the first read voltage; and
when the data in the one or more fourth memory locations is successfully decoded using the first read voltage, identifying the data in the one or more fourth memory locations as the first data.

17. The method of claim 11 , comprising: periodically updating at least one LLR of the LLRs, based on one or more decode operations performed on data stored in the one or more second memory locations.

18. An apparatus, comprising:
means for receiving first data from one or more first memory locations;
means for performing a plurality of reads for one or more memory cells at the one or more first memory locations;
means for obtaining read values based on the plurality of reads;
means for determining log likelihood ratios (LLRs) based on the first data and the read values;
means for selecting, for one or more second memory locations, one or more LLRs from the LLRs, based on an association between the one or more second memory locations and the one or more first memory locations; and
means for decoding second data from the one or more second memory locations using the selected one or more LLRs.

19. The apparatus of claim 18 , comprising: means for determining that the one or more second memory locations are associated with the one or more first memory locations.

20. The apparatus of claim 18 , wherein the means for determining that the one or more second memory locations are associated with the one or more first memory locations comprises means for determining that the one or more second memory locations are located in physical proximity to the one or more first memory locations, and wherein the ph

Assignees

• Western Digital Tech Inc

Inventors

• Lu Guangming
• Anderson Kent D
• Krishnan Anantha Raman
• Dahandeh Shafa

Classifications

• G06F11/10

  Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's · CPC title

• G06F11/1012 Primary

  using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence) · CPC title