Image sensor

Patent metadata

Field	Value
Publication number	US-11627267-B2
Application number	US-201917251004-A
Country	US
Kind code	B2
Filing date	Jun 12, 2019
Priority date	Jun 12, 2018
Publication date	Apr 11, 2023
Grant date	Apr 11, 2023

Abstract

The disclosure relates to active pixel sensors such as CMOS sensors. A sample stage of each pixel may comprise first and second sample switches in series between a buffer amplifier and a storage node. The first sample switch is connected to a column sample line, and the second sample switch is connected to a row sample line, such that an exposure signal is only passed to the storage node at a time when both a column sample signal and a row sample signal are active.

First claim

The invention claimed is:

1. An apparatus comprising: a plurality of pixels arranged in rows and columns, a plurality of column sample lines each connected to pixels of a different column, and a plurality of row sample lines each connected to pixels of a different row, each pixel comprising: a photo sensor arranged to generate an exposure signal representative of radiation incident on the pixel during an integration period; a sense node arranged to receive the exposure signal from the photodiode; a buffer amplifier arranged to receive the exposure signal from the sense node; a storage node arranged to store the exposure signal output from the buffer amplifier; a sample stage disposed between the buffer amplifier and the storage node and arranged to select whether the exposure signal is passed to the storage node; and a readout stage arranged to provide readout of the exposure signal from the pixel, the sample stage of each pixel comprising: first and second sample switches in series between the buffer amplifier and the storage node of the pixel, the first sample switch being connected to the column sample line of the pixel and the second sample switch being connected to the row sample line of the pixel, such that the exposure signal is only passed to the storage node at a time when both a COLUMN SAMPLE signal on the column sample line and a ROW SAMPLE signal on the row sample line are active.

2. The apparatus of claim 1 wherein each pixel further comprises a reset structure connected to the sense node, the reset structure arranged to reset the photo sensor and the sense node when a RESET signal to the pixel is active.

3. The apparatus of claim 2 further comprising a plurality of reset lines, each reset line being connected to the pixels of a different row, and wherein for each pixel the sample switch closest in series to the storage node is connected to the row sample line, and the sample switch closest in series to the buffer amplifier is connected to the column sample line.

4. The apparatus of claim 1 wherein the photo sensor of each pixel is a partially pinned photo diode.

5. The apparatus of claim 1 wherein the buffer amplifier of each pixel comprises a transistor arranged as a source follower responsive to the exposure signal at the sense node, and the first and second sample switches are transistors in series between an output of the buffer amplifier and the storage node.

6. The apparatus of claim 5 , arranged such that the BIAS ON signal for a pixel is active for a pixel at least when the COLUMN SAMPLE and ROW SAMPLE signals are active for selecting that pixel.

7. The apparatus of claim 6 arranged such that, during operation of the apparatus, the BIAS ON signal is always inactive for at least one third of the pixels.

8. The apparatus of claim 1 wherein the buffer amplifier of each pixel is provided with a bias current by a bias structure within the pixel, the bias structure comprising a bias switch arranged to turn on the bias current to the buffer amplifier when activated by a BIAS ON signal from outside the pixel.

9. The apparatus of claim 8 wherein the bias structure of each pixel comprises a bias transistor connected to a corresponding transistor outside the pixel to form a current mirror for providing the bias current to the buffer amplifier of the pixel.

10. The apparatus of claim 1 wherein the storage node of each pixel comprises one or more of: an NMOS capacitor; a MIM capacitor; and a metal fringe capacitor.

11. The apparatus of claim 1 further comprising a second storage node arranged to store the exposure signal output from the buffer amplifier, and a second sample stage disposed between the buffer amplifier and the second storage node and arranged to select whether the exposure signal is passed to the second storage node, the readout stage being arranged to provide readout from the pixel of the exposure signals from both the storage node and the second storage node.

12. The apparatus of claim 1 , configured such that the pixels comprise a plurality of mutually exclusive subsets of the pixels, and configured to generate the COLUMN SAMPLE and ROW SAMPLE signals, and if dependent on claim 2 also the RESET signals, such that the exposure signals for readout from the storage nodes represent a different integration period for the pixels of each subset.

13. The apparatus of claim 12 configured to generate the COLUMN SAMPLE and ROW SAMPLE signals such that transfer of the exposure signal from the buffer amplifier to the storage node ceases at substantially the same time for all pixels of each of the subsets, but at a different time for each subset.

14. The apparatus of claim 12 arranged such that the integration periods for the subsets of pixels are non-overlapping.

15. The apparatus of claim 12 , configured such that each subset of pixels is interleaved with each of the other subsets.

16. The apparatus of claim 12 wherein each subset of pixels extends over substantially the whole of the plurality of pixels.

17. The apparatus of claim 12 configured such that transfer of the exposure signal for each pixel from the buffer amplifier to the storage node ceases by the ROW SAMPLE signal becoming inactive before the COLUMN SAMPLE signal becomes inactive.

18. The apparatus of claim 12 arranged such that the readout from the pixels of the exposure signals is deferred until the exposure signals for all of the subsets of pixels have been transferred to the respective storage nodes.

19. A method of operating an active pixel sensor comprising a plurality of pixels arranged in rows and columns, each pixel comprising first and second switches in series between a sense node arranged to receive an exposure signal from a photo sensor, and a storage node for storing the exposure signal, wherein the first switches of each column of pixels are connected in common to a corresponding column sample line for control, and the second switches of each row of pixels are connected in common to a corresponding row sample line for control, the method comprising:
defining a plurality of mutually exclusive subsets of the pixels;
controlling the first and second switches such that, for each subset, the exposure signals from all pixels of the subset are transferred to the respective storage nodes of those pixels at substantially the same integration period end time, the integration period end time for each subset being different; and
reading out the exposure signals for each the subsets only after the integration period end times of all of the subsets.

20. The method of claim 19 wherein the active pixel sensor further comprises a plurality of reset lines, each row of pixels being connected in common to a corresponding reset line for reset, the series switch in each pixel closest in series to the storage node is connected to the row sample line for that pixel, and controlling the first and second switches comprises defining the integration end time for each pixel by turning off the series switch closest in series to the storage node before turning off the series switch furthest in series to the storage node.

21. The method of claim 19 wherein the subsets of the pixels are interleaved.

22. The method of claim 19 further comprising forming a series of sequential image frames, each image frame being formed using the read out exposure signals from a different one of the subsets of pixels.

Assignees

• Res & Innovation Uk

Inventors

• Scott Andrew

Classifications

• H04N25/78

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title

• H04N25/77

  Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components · CPC title

• H04N25/40

  Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled · CPC title

• H04N25/771 Primary

  comprising storage means other than floating diffusion · CPC title

• H04N25/766

  comprising control or output lines used for a plurality of functions, e.g. for pixel output, driving, reset or power · CPC title