Multiplicative masking for cryptographic operations

Patent metadata

Field	Value
Publication number	US-11626970-B2
Application number	US-201515533974-A
Country	US
Kind code	B2
Filing date	Dec 3, 2015
Priority date	Dec 8, 2014
Publication date	Apr 11, 2023
Grant date	Apr 11, 2023

Abstract

A value corresponding to an input for a cryptographic operation may be received. The value may be masked by multiplying the value with a first number modulo a prime number. The cryptographic operation may subsequently be performed on the masked value.

First claim

What is claimed is:

1. A method to perform a cryptographic operation on a plaintext input, the method comprising:
receiving an input value corresponding to the plaintext input into the cryptographic operation;
obtaining an incremented value by incrementing at least a part of the input value;
generating a first number based on a range of values that is associated with a prime number;
obtaining, by a processing device, a masked value by multiplying the incremented value by the first number modulo the prime number; and
performing the cryptographic operation based on the masked value.

2. The method of claim 1 , wherein obtaining the incremented value comprises incrementing a half portion of the input value.

3. The method of claim 1 , wherein the first number is a randomly generated number that is at a value less than the prime number.

4. The method of claim 1 , wherein the incremented part of the input value is a one-bit value, and wherein obtaining the incremented value comprises:
incrementing the one-bit value by one of a positive number or a negative number, if the one-bit value is 0; or
incrementing the one-bit value by the other of the positive number or the negative number, if the one-bit value is 1.

5. The method of claim 4 , wherein the positive number is a randomly selected positive number and the negative number has the same absolute value as the positive number.

6. The method of claim 1 , further comprising:
in response to obtaining the masked value, performing a second modulus operation that returns a value of zero.

7. The method of claim 6 , wherein the modulus operation is associated with power consumption to reduce susceptibility of a Differential Power Analysis (DPA) leak.

8. The method of claim 1 , wherein the prime number is a divisor of a modulus operation, wherein a dividend of the modulus operation is at least partly based on the first number, and wherein the modulus operation returns a non-zero value.

9. The method of claim 1 , where the cryptographic operation is associated with a logical exclusive-or (XOR) operation that is performed between the masked value and a second masked value corresponding to a second input, and wherein the logical to XOR operation is performed by:
multiplying a combination of the masked value and the second masked value with an inverse of another value that is used in the masking of inputs of the cryptographic operation to generate an intermediate value; and
performing an operation corresponding to the intermediate value modulo the prime number.

10. The method of claim 1 , where the cryptographic operation is associated with a logical AND operation that is performed between the masked value and a second masked value corresponding to a second input, and wherein the logical AND operation is performed by:
adding, to each of the masked value and the second masked value, another value that is used in the masking of inputs of the cryptographic operation to generate an intermediate value;
multiplying an inverse of the another value that is used in the masking of inputs of the cryptographic operation and an inverse of two with the intermediate value; and
subtracting, from results of the multiplying, a value corresponding to the another value that is used in the masking of inputs modulo the prime number.

11. A system comprising:
a memory; and
a processing device operatively coupled with the memory and to:
receive an input value corresponding to a plaintext input into a cryptographic operation;
obtain an incremented value by incrementing at least part of the input value;
generate a first number based on a range of values that is associated with a prime number;
obtain a masked value by multiplying the incremented value by the first number modulo the prime number; and
perform the cryptographic operation based on the masked value.

12. The system of claim 11 , wherein to obtain the incremented value the processing device is to increment a half portion of the input value.

13. The system of claim 11 , wherein the first number is a randomly generated number that is at a value less than the prime number.

14. The system of claim 11 , wherein the incremented part of the input is a one-bit value, and wherein to obtain the incremented value the processing device is to:
incrementing the one-bit value by one of a positive number or a negative number, if the one-bit value is 0; or
incrementing the one-bit value by the other of the positive number or the negative number, if the one-bit value is 1.

15. The system of claim 14 , wherein the positive number is a randomly selected positive number and the negative number has the same absolute value as the positive number.

16. The system of claim 11 , wherein the processing device is further to:
in response to obtaining the masked value, perform a second modulus operation that returns a value of zero.

17. The system of claim 16 , wherein the modulus operation is associated with power consumption to reduce susceptibility of a Differential Power Analysis (DPA) leak.

18. The system of claim 11 , wherein the prime number is a divisor of a modulus operation, wherein a dividend of the modulus operation is at least partly based on the first number, and wherein the modulus operation returns a non-zero value.

19. The system of claim 11 , where the cryptographic operation is associated with a logical exclusive-or (XOR) operation that is performed between the masked value and a second masked value corresponding to a second input, and wherein the logical XOR operation is performed by:
multiplying a combination of the masked value and the second masked value with an inverse of another value that is used in the masking of inputs of the cryptographic operation to generate an intermediate value; and
performing an operation corresponding to the intermediate value modulo the prime number.

20. The system of claim 11 , where the cryptographic operation is associated with a logical AND operation that is performed between the masked value and a second masked value corresponding to a second input, and wherein the logical AND operation is performed by:
adding, to each of the masked value and the second masked value, another value that is used in the masking of inputs of the cryptographic operation to generate an intermediate value;
multiplying an inverse of the another value that is used in the masking of inputs of the cryptographic operation and an inverse of two with the intermediate value; and
subtracting, from results of the multiplying, a value corresponding to the another value that is used in the masking of inputs modulo the prime number.

21. A non-transitory computer readable medium including data that, when accessed by a processing device, cause the processing device to perform operations comprising:
receiving an input value corresponding to a plaintext input into a cryptographic operation;
obtaining an incremented value by incrementing at least a part of the input value;
generating a first number based on a range of values that is associated with a prime number;
obtaining a masked value by multiplying the incremented value by the first number modulo the prime number; and
performing the cryptographic operation based on the masked value.

22. The non-transitory computer readable medium of claim 21 , wherein obtaining the incremented value comprises incrementing a half portion of the input value.

23. The non-transitory computer readable medium of claim 21 , where

Assignees

• Cryptography Res Inc

Inventors

• Tunstall Michael
• Durvaux Jr Francois

Classifications

• H04L2209/08

  Randomization, e.g. dummy operations or using noise · CPC title

• H04L2209/046

  of operations, operands or results of the operations · CPC title

• H04L9/003 Primary

  for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA] · CPC title

• G06F21/71

  to assure secure computing or processing of information · CPC title