Per-pixel detector bias control

Patent metadata

Field	Value
Publication number	US-11626445-B2
Application number	US-201916549069-A
Country	US
Kind code	B2
Filing date	Aug 23, 2019
Priority date	Aug 23, 2018
Publication date	Apr 11, 2023
Grant date	Apr 11, 2023

Abstract

A pixel includes a photo-diode, an integration capacitor arranged to receive a photo current from the photo-diode and to store charge developed from the photo current; and an injection transistor disposed between the photo-diode and the integration capacitor that controls flow of the photo current from the photo-diode to the integration capacitor, the injection transistor having a gate, a source electrically coupled to the photo-diode at a first node, and a drain electrically coupled to the integration capacitor. The injection transistor is a silicon-oxide-nitride-oxide-silicon (SONOS) FET having its gate set to a SONOS gate voltage to control a detector bias voltage of the photo-diode at the first node.

First claim

What is claimed is:

1. A pixel comprising:
a photo-diode;
an integration capacitor arranged to receive a photo current from the photo-diode and to store charge developed from the photo current; and
an injection transistor formed as a silicon-oxide-nitride-oxide-silicon (SONOS) FET coupled to the photo-diode and the integration capacitor and that controls a detector bias of the photo-diode, the injection transistor having a gate, a source electrically coupled to the photo-diode at a first node, and a drain electrically coupled to the integration capacitor;
wherein the gate is set to a SONOS gate voltage to control the detector bias voltage of the photo-diode at the first node.

2. The pixel of claim 1 , wherein the detector bias voltage at the first node is equal to:
V DETBIAS =V dd −( V TSONOS −V GS );

where V GS is the gate to source voltage of the injection transistor, V TSONOS is the SONOS gate voltage, and V dd is a voltage applied on a side of the photo-diode opposite the first node.

3. The pixel of claim 1 , wherein the gate is formed of a gate stack that includes a layer of silicon nitride that stores current to set the SONOS gate voltage.

4. The pixel of claim 3 , wherein the layer of silicon nitride is formed of Si 3 N 4 or Si 9 N 10 .

5. The pixel of claim 1 , further including a reset switch coupled in parallel with the integration capacitor.

6. A method of operating a pixel, the method comprising:
coupling a photo-diode to a source of an injection transistor, wherein the injection transistor is a silicon-oxide-nitride-oxide-silicon (SONOS) FET;
coupling an integration capacitor to a drain of the injection transistor such that the integration capacitor can receive a photo current from the photo-diode that passes through the injection transistor and store charge developed from the photo current; and
setting a SONOS gate voltage on the injection transistor to control a detector bias voltage of the photo-diode at a first node disposed between the photo-diode and the integration capacitor.

7. The method of claim 6 , wherein the detector bias voltage at the first node is equal to:
V DETBIAS =V dd −( V TSONOS −V GS );

where V GS is the gate to source voltage of the injection transistor, V TSONOS is the SONOS gate voltage, and V dd is a voltage applied on a side of the photo-diode opposite the first node.

8. The method of claim 6 , wherein the gate is formed of a gate stack that includes a layer of silicon nitride that stores current to set the SONOS gate voltage.

9. The method of claim 8 , wherein the layer of silicon nitride is formed of Si 3 N 4 or Si 9 N 10 .

10. The method of claim 6 , wherein setting the SONOS gate voltage includes providing a pulse to the gate of the injection transistor, wherein the length of pulse is proportional to the level of the SONOS gate voltage.

11. A pixel comprising:
a photo-diode;
an integration capacitor arranged to receive a current from the photo-diode and to store charge developed from the current; and
a silicon-oxide-nitride-oxide-silicon (SONOS) field-effect transistor (FET) coupled to the the photodiode and to the integration capacitor such that current from the photo-diode passes through the SONOS FET to reach the integration capacitor, wherein the SONOS FET is configured to control a detector bias voltage of the photo-diode.

12. The pixel of claim 11 , wherein the SONOS FET comprises a gate, a source electrically coupled to the photodiode at a first node, and a drain electrically coupled to the integration capacitor, wherein the gate is set to a SONOS gate voltage to control the detector bias voltage of the photo-diode at the first node.

13. The pixel of claim 12 , wherein the detector bias voltage at the first node is equal to:
V DETBIAS =V dd −( V TSONOS −V GS );

where V GS is the gate to source voltage of the injection transistor, V TSONOS is the SONOS gate voltage, and V dd is a voltage applied on a side of the photo-diode opposite the first node.

14. The pixel of claim 12 , wherein the gate is formed of a gate stack that includes a layer of silicon nitride that stores current to set the SONOS gate voltage.

15. The pixel of claim 14 , wherein the layer of silicon nitride is formed of Si 3 N 4 or Si 9 N 10 .

16. The pixel of claim 11 , further including a reset switch coupled in parallel with the integration capacitor.

Assignees

• Raytheon Co

Inventors

• Beuville Eric J
• Harris Micky
• Boesch Ryan
• Boemler Christian M

Classifications

• H04N25/671

  for non-uniformity detection or correction · CPC title

• H04N25/626

  Reduction of noise due to residual charges remaining after image readout, e.g. to remove ghost images or afterimages · CPC title

• H10D30/69 Primary

  IGFETs having charge trapping gate insulators, e.g. MNOS transistors · CPC title

• H10F39/18 Primary

  Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors · CPC title

• H10F39/15

  Charge-coupled device [CCD] image sensors · CPC title