Chip resistor and method for manufacturing same

US11626219B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11626219-B2
Application numberUS-202217584788-A
CountryUS
Kind codeB2
Filing dateJan 26, 2022
Priority dateJan 15, 2021
Publication dateApr 11, 2023
Grant dateApr 11, 2023

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A glass protective film 4 is formed such that boundaries of top surface electrodes 3a and 3b do not exist at the base of corner portions of the rectangular glass protective film 4 so as to eliminate level differences generating due to thicknesses of the electrodes. Use of such a structure may resolve the problem that when printing glass paste individually over chip elements of a chip resistor on a large substrate from which multiple chips will be obtained, corner portions of the glass protective film bleed (flow) to the outer side (dividing grooves).

First claim

Opening claim text (preview).

The invention claimed is: 1. A chip resistor comprising: a rectangular parallelepiped insulation substrate; paired top surface electrodes arranged facing each other at predetermined intervals at either longitudinal end part on the top surface of the insulation substrate; a resistive element formed between the paired top surface electrodes; and a rectangular protective film covering a predetermined region of the insulation substrate; wherein the predetermined region is a region including the entire top surface of the resistive element and connection regions of the resistive element and the paired top surface electrodes, and the protective film is formed so as for four corner portions of the protective film in plan view to not overlap the paired top surface electrodes, and so as to avoid either longitudinal end part on the top surface of the insulation substrate, wherein the paired top surface electrodes each comprise an extension part having a wider width than that of the resistive element in the lateral direction of the insulation substrate at the connection regions, and other regions excluding the extension parts have substantially the same width as that of the resistive element. 2. The chip resistor according to claim 1 , wherein the width of the extension parts gradually changes so as to approach the width of the resistive element the further toward either longitudinal end part of the insulation substrate. 3. The chip resistor according to claim 1 , wherein the protective film is a glass protective film. 4. A chip resistor manufacturing method, comprising the steps of: forming latticed primary dividing grooves and secondary dividing grooves orthogonal to each other on the top surface of a large insulation substrate from which multiple chip resistors are obtained; forming multiple electrodes facing each other at predetermined intervals in multiple predetermined regions divided by the primary and the secondary dividing grooves on the top surface of the large insulation substrate; forming multiple resistive elements respectively stretching over the multiple electrodes arranged facing each other; forming a rectangular glass protective film for individually covering regions including the entire top surfaces of the respective multiple resistive elements and connection regions of the multiple resistive elements with the respective multiple electrodes; forming a trimming groove in the respective multiple resistive elements after the glass protective film is formed, so as to adjust resistance values; dividing the large insulation substrate along the primary dividing grooves so as to obtain strip substrates; forming end electrodes on side surfaces of the strip substrates; and dividing the strip substrates, on which the end electrodes are formed, along the secondary dividing grooves so as to obtain chip resistive elements; wherein the glass protective film is formed so as for four corner portions of the glass protective film in plan view to not overlap the respective multiple electrodes, and so as to avoid the secondary dividing grooves, wherein the multiple electrodes each comprise an extension part having a wider width than that of each of the multiple resistive elements in the direction of the primary dividing grooves at each of the connection regions, and other regions excluding the extension parts have substantially the same width as that of each of the multiple resistive elements. 5. The chip resistor manufacturing method according to claim 4 , further comprising the step of forming multiple resin protective films extending in a belt-like form along the primary dividing grooves.

Assignees

Inventors

Classifications

  • adapted for manufacturing resistor chips · CPC title

  • H01C1/14Primary

    Terminals or tapping points specially adapted for resistors; Arrangements of terminals or tapping points on resistors · CPC title

  • adapted for trimming · CPC title

  • Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material (consisting of loose powdered or granular material H01C8/00; resistors having potential barriers, e.g. field-effect resistors, H10D1/40 - H10D1/43, H10K10/10; semiconductor devices sensitive to electromagnetic or corpuscular radiation, e.g. photoresistors, H10F30/00; magnetic field controlled resistors H10N50/10; bulk negative resistance effect devices H10N80/00) · CPC title

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What does patent US11626219B2 cover?
A glass protective film 4 is formed such that boundaries of top surface electrodes 3a and 3b do not exist at the base of corner portions of the rectangular glass protective film 4 so as to eliminate level differences generating due to thicknesses of the electrodes. Use of such a structure may resolve the problem that when printing glass paste individually over chip elements of a chip resistor o…
Who is the assignee on this patent?
Koa Corp
What technology area does this patent fall under?
Primary CPC classification H01C1/14. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 11 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).