Memory device

Patent metadata

Field	Value
Publication number	US-11626165-B2
Application number	US-202217888743-A
Country	US
Kind code	B2
Filing date	Aug 16, 2022
Priority date	Sep 22, 2020
Publication date	Apr 11, 2023
Grant date	Apr 11, 2023

Abstract

A memory device includes a cell area including memory blocks, and a peripheral circuit area including peripheral circuits that execute an erase operation for each of the memory blocks. Each memory block includes word lines that are stacked on a substrate, channel structures penetrate through the word lines, and a source region that is disposed on the substrate and connected to the channel structures. During the erase operation in which an erase voltage is provided to the source region of a target memory block among the memory blocks, the peripheral circuits reduce a voltage of a first word line from a first bias voltage to a second bias voltage at a first time, and to reduce a voltage of a second word line, different from the first word line, from a third bias voltage to a fourth bias voltage at a second time different from the first time.

First claim

What is claimed is:

1. A memory device comprising:
a cell area in which a plurality of memory blocks, each including a plurality of memory cells, are disposed; and
a peripheral circuit area including peripheral circuits that control the plurality of memory blocks and that are configured to execute an erase operation for each of the plurality of memory blocks as a unit,
wherein each of the plurality of memory blocks includes a plurality of word lines that are stacked on a substrate, a plurality of channel structures that extend in a first direction perpendicular to an upper surface of the substrate and that penetrate through the plurality of word lines, and a source region that is disposed on the substrate and connected to the plurality of channel structures,
the plurality of word lines include a plurality of lower word lines stacked on the substrate and a plurality of upper word lines stacked on the plurality of lower word lines,
each of the plurality of channel structures includes a lower channel structure penetrating the plurality of lower word lines and an upper channel structure penetrating the plurality of upper word lines and connected to the lower channel structure, and
during the erase operation in which an erase voltage is provided to the source region of a target memory block among the plurality of memory blocks, the peripheral circuits are configured to reduce a voltage of a first word line from a first bias voltage to a second bias voltage at a first time, and to reduce a voltage of a second word line, different from the first word line, from a third bias voltage to a fourth bias voltage at a second time different from the first time.

2. The memory device of claim 1 , wherein a diameter of the upper channel structure adjacent to the first word line is smaller than a diameter of the lower channel structure adjacent to the second word line, and
the first time is later than the second time.

3. The memory device of claim 2 , wherein a number of a portion of the plurality of upper word lines disposed between the first word line and a boundary between the lower channel structure and the upper channel structure is less than a number of a portion of the plurality of lower word lines disposed between the second word line and the upper surface of the substrate.

4. The memory device of claim 1 , wherein the first bias voltage is different than the third bias voltage.

5. The memory device of claim 1 , wherein the second bias voltage is different than the fourth bias voltage.

6. The memory device of claim 1 , wherein an erase time in which the erase operation is executed includes a transition period in which a voltage of the source region increases to the erase voltage, and a hold period in which the voltage of the source region is maintained at the erase voltage, and
the first time and the second time are later than an ending time of the transition period.

7. The memory device of claim 6 , wherein each of the plurality of memory blocks includes a plurality of string selection lines disposed above the plurality of word lines and a ground selection line disposed below the plurality of word lines, and
the peripheral circuits are configured to turn off the plurality of string selection lines until a first turn-on point that is in the transition period and to input a first suppression voltage to the plurality of string selection lines after the first turn-on point, and are configured to turn off the ground selection line until a second turn-on point that is in the transition period and to input a second suppression voltage to the ground selection line after the second turn-on point.

8. The memory device of claim 7 , wherein a level the first suppression voltage and the second suppression voltage are greater than the first bias voltage and the third bias voltage.

9. The memory device of claim 8 , wherein a level of each of the first suppression voltage and the second suppression voltage is greater than a level of the first bias voltage and a level of the third bias voltage.

10. The memory device of claim 6 , wherein the peripheral circuits include a plurality of pass elements connected to the plurality of word lines, and are configured to sequentially input a first turn-on voltage and a second turn-on voltage less than the first turn-on voltage to a gate terminal of each of the plurality of pass elements, during the erase operation.

11. The memory device of claim 10 , wherein a time at which the second turn-on voltage is input to the gate terminal of each of the plurality of pass elements belongs to the hold period.

12. The memory device of claim 11 , wherein the time at which the second turn-on voltage is input to the gate terminal of each of the plurality of pass elements is earlier than the first time and the second time.

13. The memory device of claim 1 , wherein the plurality of upper word lines include the first word line and a third word line disposed above the first word line, and the plurality of lower word lines include the second word line and a fourth word line disposed below the second word line, and
the peripheral circuits reduce a voltage of the third word line from the first bias voltage to the second bias voltage at a third time different from the first time, and reduces a voltage of the fourth word line from the third bias voltage to the fourth bias voltage at a fourth time different from the second time.

14. The memory device of claim 13 , wherein the third time is earlier than the first time, and the fourth time is later than the second time.

15. The memory device of claim 1 , wherein the substrate included in the cell area is a first substrate, and the peripheral circuit area includes a second substrate on which the peripheral circuits are disposed and which is different from the first substrate,
the cell area includes a plurality of upper bonding metals connected to the plurality of word lines, and
the peripheral circuit area includes a plurality of lower bonding metals bonded directly to the plurality of upper bonding metals, and a row decoder connected to the plurality of lower bonding metals and configured to determine a voltage of each of the plurality of word lines.

16. A memory device comprising:
a cell area in which a plurality of memory blocks are disposed, each of the plurality of memory blocks includes a plurality of memory cells; and
a peripheral circuit area including peripheral circuits that control the plurality of memory blocks,
wherein each of the plurality of memory blocks is connected to the peripheral circuits by a plurality of word lines, a plurality of string select lines, at least one ground select line, at least one common source line, a plurality of erase control lines, and a plurality of bit lines,
an erase operation for a target memory block among the plurality of memory blocks includes a transition period in which the peripheral circuits increase a voltage of the at least one common source line to an erase voltage, and a hold period in which the peripheral circuits maintain the voltage of the at least one common source line as the erase voltage,
the peripheral circuits float the plurality of erase control lines and input a suppression voltage to the at least one ground select line and the plurality of string select lines after a delay time elapses in the transition period, and
the peripheral circuits reduce a voltage of a first word line among the plurality of word lines at a first time, and reduce a voltage of a second word line different from the first word line at a second time different from the first time.

17. The mem

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Yohan
• Nam Sangwan
• Park Sangwon

Classifications

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/08 Primary

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/3445

  Circuits or methods to verify correct erasure of nonvolatile memory cells · CPC title

• G11C16/32

  Timing circuits · CPC title

• G11C8/14

  Word line organisation; Word line lay-out · CPC title