Display module test platform

US11624788B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11624788-B2
Application numberUS-202016831858-A
CountryUS
Kind codeB2
Filing dateMar 27, 2020
Priority dateSep 19, 2018
Publication dateApr 11, 2023
Grant dateApr 11, 2023

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present application relates to the field of display technology, and discloses a display module test platform, including a core processor. The core processor is capable of supporting installation of a terminal operating system. A display output terminal of the core processor is connected to a display module to be tested. The display module to be tested includes a touch structure. The touch structure and the core processor communicate with each other via an Inter-Integrated Circuit (I2C) bus.

First claim

Opening claim text (preview).

The invention claimed is: 1. A display module test platform, comprising: a core processor, supporting installation of a terminal operating system, wherein a display output terminal of the core processor is connected to a display module to be tested, the display module to be tested comprises a touch structure, and the touch structure and the core processor communicate with each other via an Inter-Integrated Circuit (I 2 C) bus, the display output terminal of the core processor is connected to the display module to be tested via a bridge module, the bridge module and the core processor are connected by the I 2 C bus, wherein the bridge module is configured to convert an Embedded Display Port (eDP) signal sent by the core processor into a Mobile Industry Processor Interface (MIPI) signal recognizable by the display module to be tested, after performing an eDP link training stage. 2. The display module test platform according to claim 1 , further comprising: a memory, connected to the core processor, and configured to store a correspondence relation between a model of a display module and configuration parameters, wherein the core processor is configured to: determine, according to the correspondence relation stored in the memory, configuration parameters corresponding to a model of the display module to be tested, and output the configuration parameters to the display module to be tested. 3. The display module test platform according to claim 1 , further comprising an acquisition module, connected to the display module to be tested and the core processor, and configured to: acquire a voltage and a current of the display module to be tested, and send the voltage and current to the core processor. 4. The display module test platform according to claim 1 , wherein the terminal operating system is any one of an Android operating system, an iOS operating system, a Windows operating system, and a Linux operating system. 5. The display module test platform according to claim 1 , further comprising: an input interface, connected to the core processor and an input device respectively, wherein the input device is configured to control the display module to be tested. 6. The display module test platform according to claim 5 , wherein the input interface is an On-The-Go interface, and the input device connected to the On-The-Go interface is a mouse and/or a keyboard. 7. The display module test platform according to claim 1 , further comprising: a Universal Asynchronous Receiver-Transmitter interface, connected to the core processor, and configured to return test information of the display module to be tested. 8. The display module test platform according to claim 1 , further comprising: a storage interface, connected to the core processor and a storage device respectively, wherein the storage device is configured to store test images and test videos. 9. The display module test platform according to claim 1 , wherein the core processor is a processor based on an Advanced Reduced Instruction Set Computing Machine architecture. 10. The display module test platform according to claim 1 , further comprising: a power supply, connected to the display module to be tested and the core processor respectively, and configured to supply power to the display module to be tested and the core processor. 11. The display module test platform according to claim 2 , further comprising an acquisition module, connected to the display module to be tested and the core processor respectively, and configured to: acquire a voltage and a current of the display module to be tested, and send the voltage and current to the core processor. 12. The display module test platform according to claim 11 , further comprising: an input interface, connected to the core processor and an input device respectively, wherein the input device is configured to control the display module to be tested. 13. The display module test platform according to claim 12 , further comprising: a Universal Asynchronous Receiver-Transmitter interface, connected to the core processor, and configured to return test information of the display module to be tested. 14. The display module test platform according to claim 13 , further comprising: a storage interface, connected to the core processor and a storage device respectively, wherein the storage device is configured to store test images and test videos. 15. The display module test platform according to claim 14 , further comprising: a power supply, connected to the display module to be tested and the core processor respectively, and configured to supply power to the display module to be tested and the core processor. 16. The display module test platform according to claim 1 , wherein the bridge module is a bridge circuit or a bridge chip. 17. The display module test platform according to claim 1 , further comprising: a power supply, connected to the bridge module to supply power to the bridge module. 18. The display module test platform according to claim 1 , further comprising: an Embedded Display Port bus, wherein the core processor loads a driver of the Embedded Display Port bus. 19. The display module test platform according to claim 1 , wherein the bridge module requests the I 2 C bus to perform initialization.

Assignees

Inventors

Classifications

  • on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

  • for inputting data by handwriting, e.g. gesture or text · CPC title

  • Live connection to bus, e.g. hot-plugging (current or voltage limitation during live insertion H02H9/004) · CPC title

  • by configuration test · CPC title

  • Calibration of display systems · CPC title

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What does patent US11624788B2 cover?
The present application relates to the field of display technology, and discloses a display module test platform, including a core processor. The core processor is capable of supporting installation of a terminal operating system. A display output terminal of the core processor is connected to a display module to be tested. The display module to be tested includes a touch structure. The touch s…
Who is the assignee on this patent?
Kunshan Govisionox Optoelectronics Co Ltd
What technology area does this patent fall under?
Primary CPC classification G06F13/4081. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Apr 11 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 7 related publications on this page (citations in our corpus or others sharing the same primary CPC).