Semiconductor device

Patent metadata

Field	Value
Publication number	US-11621320-B2
Application number	US-202117389024-A
Country	US
Kind code	B2
Filing date	Jul 29, 2021
Priority date	Sep 3, 2020
Publication date	Apr 4, 2023
Grant date	Apr 4, 2023

Abstract

A main semiconductor device element is SiC-MOSFETs with a trench gate structure, the main semiconductor device element having main MOS regions responsible for driving the MOSFETs and main SBD regions that are regions responsible for SBD operation. The main MOS regions and the main SBD regions are adjacent to one another and each pair of a main MOS region and a main SBD region adjacent thereto share one trench. In the main SBD regions, first and second p-type regions, and Schottky electrodes at the front surface of the semiconductor substrate and forming Schottky junctions with an n−-type drift region are provided. The first p-type regions are provided along sidewalls of the trenches, in contact with the first p+-type regions at the bottoms of the trenches. The second p-type regions are provided between the first p-type regions and the Schottky electrodes, and are electrically connected to these regions.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor substrate containing a semiconductor having a bandgap wider than a bandgap of silicon, the semiconductor substrate having a first main surface and a second main surface opposite to each other;
a first semiconductor region of a first conductivity type, provided in the semiconductor substrate, at the first main surface of the semiconductor substrate;
a plurality of second semiconductor regions of a second conductivity type, selectively provided between the first main surface of the semiconductor substrate and the first semiconductor region;
a plurality of third semiconductor regions of the first conductivity type, selectively provided between the first main surface of the semiconductor substrate and the second semiconductor regions, the third semiconductor regions having an impurity concentration higher than an impurity concentration of the first semiconductor region;
a plurality of trenches penetrating through the third semiconductor regions and the second semiconductor regions, and reaching the first semiconductor region;
a plurality of gate electrodes that are respectively provided in the trenches via a respective one of a plurality of gate insulating films;
a plurality of first high-concentration regions of the second conductivity type, selectively provided in the first semiconductor region, the first high-concentration regions, in a depth direction, respectively facing and surrounding bottoms of the trenches, the first high-concentration regions having an impurity concentration higher than an impurity concentration of the second semiconductor regions;
a plurality of second high-concentration regions of the second conductivity type, selectively provided in the first semiconductor region, separate from the first high-concentration regions and the trenches, and in contact with the second semiconductor regions, bottoms of the second high-concentration regions being located at positions deeper from the second semiconductor regions than are positions of the bottoms of the trenches, the second high-concentration regions having an impurity concentration higher than the impurity concentration of the second semiconductor regions;
a first electrode provided on the first main surface of the semiconductor substrate, in ohmic contact with the third semiconductor regions between a first adjacent two of the trenches that are adjacent to each other;
a first Schottky electrode provided on the first main surface of the semiconductor substrate, between a second adjacent two of the trenches that are adjacent each other, the first Schottky electrode electrically connected to the first electrode and forming a Schottky junction with the first semiconductor region;
a plurality of fourth semiconductor regions of the second conductivity type, respectively provided between each of the second adjacent two of the trenches and the first semiconductor region, each fourth semiconductor region extending in the depth direction along a sidewall of said each of the second adjacent two of the trenches, from the first main surface toward the second main surface of the semiconductor substrate, and contacting a corresponding one of the first high-concentration regions;
a plurality of fifth semiconductor regions of the second conductivity type respectively provided between respective ones of the fourth semiconductor regions and the first semiconductor region, each fifth semiconductor region being in contact with a respective one of the fourth semiconductor regions, the first semiconductor region and the first Schottky electrode; and
a second electrode provided on the second main surface of the semiconductor substrate.

2. The semiconductor device according to claim 1 , wherein bottoms of the fifth semiconductor regions are located at positions shallower from the first main surface of the semiconductor substrate in the depth direction than are positions of bottoms of the fourth semiconductor regions.

3. The semiconductor device according to claim 1 , further comprising
a third high-concentration region of the second conductivity type, selectively provided between the second adjacent two of the trenches, below the first Schottky electrode, the third high-concentration region being provided in the first semiconductor region, separate from the first high-concentration regions and the trenches, a bottom of the third high-concentration region being located at a position deeper than are the positions of the bottoms of the trenches, the third high-concentration region having an impurity concentration higher than the impurity concentration of the second semiconductor regions.

4. The semiconductor device according to claim 1 , further comprising
a lifetime killer region provided between the first adjacent two of the trenches including an entire area in which a corresponding one of the second high-concentration regions is provided, the lifetime killer region extending in a direction orthogonal to a direction of the trenches, to reach corresponding ones of the first high-concentration regions that respectively face one of the first adjacent two of the trenches, at a position deeper than are the positions of the bottoms of the trenches.

5. The semiconductor device according to claim 1 , wherein the plurality of fourth semiconductor regions and the corresponding one of the first high-concentration regions surround sidewalls of the second adjacent two of the trenches that face each other.

6. The semiconductor device according to claim 1 , further comprising
a current sensing portion having a current sensing region that detects current flowing from the second electrode to the first electrode, and a first protective region surrounding the current sensing region, wherein
the current sensing region has:
a plurality of sixth semiconductor regions of the second conductivity type, selectively provided between the first main surface of the semiconductor substrate and the first semiconductor region, in regions different than positions of the second semiconductor regions,
a third electrode provided on the first main surface of the semiconductor substrate and electrically connected to the sixth semiconductor regions, and
a plurality of insulated gate field effect transistors, each of which uses the first semiconductor region as a drift region, a respective one of the sixth semiconductor regions as a base region, the third electrode as a source electrode, and the second electrode as a drain electrode,
a second Schottky electrode forming a Schottky junction with the first semiconductor region, provided on the first main surface of the semiconductor substrate, in the first protective region, wherein

the second Schottky electrode has a closed curve shape surrounding a periphery of the current sensing region and is electrically connected to the third electrode.

7. The semiconductor device according to claim 6 , wherein
the current sensing portion further includes a second protective region surrounding a periphery of the first protective region, and
a plurality of seventh semiconductor regions of the second conductivity type, fixed to a potential of the third electrode is provided in the second protective region, between the first main surface of the semiconductor substrate and the first semiconductor region, separate from the second semiconductor regions and the sixth semiconductor regions.

8. The semiconductor device according to claim 1 , further comprising a current spreading layer of the first conductivity type, provided between the first adjacent two of the trenches, and between the first semiconductor region and the second semiconductor regions, the current spreading layer having an impurity concentration higher than the impuri

Assignees

• Fuji Electric Co Ltd

Inventors

• Hoshi Yasuyuki

Classifications

• H10D30/0297

  using recessing of the gate electrodes, e.g. to form trench gate electrodes · CPC title

• H10D84/146

  the built-in components being Schottky barrier diodes · CPC title

• H10D8/60

  Schottky-barrier diodes · CPC title

• H10D30/669

  having voltage-sensing or current-sensing structures, e.g. emulator sections or overcurrent sensing cells · CPC title

• H10D84/143

  the built-in components being PN junction diodes · CPC title