Capacitor unit

Patent metadata

Field	Value
Publication number	US-11621128-B2
Application number	US-202117523824-A
Country	US
Kind code	B2
Filing date	Nov 10, 2021
Priority date	Nov 5, 2018
Publication date	Apr 4, 2023
Grant date	Apr 4, 2023

Abstract

A capacitor unit formed by a capacitor integrated structure is provided. The capacitor integrated structure is cut to form capacitor units separated from each other, and each of the capacitor units includes: a substrate; an isolation layer located on the substrate; a capacitor stacked structure located on the isolation layer, wherein the isolation layer electrically isolates the substrate from the capacitor stacked structure; and two electrode connectors located on the capacitor stacked structure and being exposed.

First claim

What is claimed is:

1. A capacitor unit, comprising:
a substrate;
an isolation layer located on the substrate;
a capacitor stacked structure located on the isolation layer, wherein the isolation layer electrically isolates the substrate from the capacitor stacked structure; and
two electrode connectors located on the capacitor stacked structure and being exposed, wherein
the capacitor stacked structure comprises:
a first conductive layer located on a portion of the isolation layer to expose a first portion of the isolation layer;
a capacitor dielectric layer located on the first conductive layer;
a second conductive layer located on a portion of the capacitor dielectric layer to expose a first portion of the capacitor dielectric layer;
an interlayer dielectric layer located on the second conductive layer, the first portion of the capacitor dielectric layer, and the first portion of the isolation layer;
a first bonding pad and a second bonding pad respectively located on the interlayer dielectric layer; and
first metal pillars and second metal pillars, wherein the first metal pillars are located in the interlayer dielectric layer and pass through the first portion of the capacitor dielectric layer to connect to the first conductive layer under the first portion of the capacitor dielectric layer, so that the first conductive layer is electrically connected to the first bonding pad by the first metal pillars to form a first electrode, and the second metal pillars are located in the interlayer dielectric layer and connect to the second conductive layer, so that the second conductive layer is electrically connected to the second bonding pad by the second metal pillars to form a second electrode.

2. The capacitor unit according to claim 1 , further comprising:
a protection layer respectively covering the first bonding pad and the second bonding pad;
a first bonding pad opening formed in the protective layer to expose the first electrode; and
a second bonding pad opening formed on the second bonding pad to expose the second electrode.

3. A capacitor unit, comprising:
a substrate;
an isolation layer located on the substrate;
a capacitor stacked structure located on the isolation layer, wherein the isolation layer electrically isolates the substrate from the capacitor stacked structure; and
two electrode connectors located on the capacitor stacked structure and being exposed, wherein
the capacitor stacked structure comprises:
a first conductive layer located on the isolation layer and exposing a first portion of the isolation layer, wherein a spacer is formed on each of two sidewalls of the first conductive layer;
a capacitor dielectric layer located on the first conductive layer and the first portion of the isolation layer, wherein the capacitor dielectric layer further comprises a third portion directly located above the isolation layer, and the capacitor dielectric layer and each of the sidewalls of the first conductive layer are isolated by the spacer;
a second conductive layer located on a portion of the capacitor dielectric layer and exposing a fourth portion of the capacitor dielectric layer above the first conductive layer;
an interlayer dielectric layer located on the second conductive layer and the fourth portion of the capacitor dielectric layer;
a first bonding pad and a second bonding pad respectively located on the interlayer dielectric layer; and
first metal pillars and second metal pillars, wherein the first metal pillars are located in the interlayer dielectric layer and pass through the fourth portion of the capacitor dielectric layer to connect to the first conductive layer under the fourth portion of the capacitor dielectric layer, so that the first conductive layer is electrically connected to the first bonding pad by the first metal pillars to form a first electrode, and the second metal pillars are located in the interlayer dielectric layer and connect to the second conductive layer above the third portion of the capacitor dielectric layer, so that the second conductive layer is electrically connected to the second bonding pad by the second metal pillars to form a second electrode.

4. A capacitor unit, comprising:
a substrate;
an isolation layer located on the substrate;
a capacitor stacked structure located on the isolation layer, wherein the isolation layer electrically isolates the substrate from the capacitor stacked structure; and
two electrode connectors located on the capacitor stacked structure and being exposed, wherein
the capacitor stacked structure comprises:
a first capacitor dielectric structure located on the isolation layer and having a first conductive layer located on the isolation layer and a first capacitor dielectric layer located on the first conductive layer, wherein the first conductive layer comprises a first left electrode and a first right electrode isolated from each other, and the first capacitor dielectric layer comprises first left openings formed above the first left electrode and first right openings formed above the first right electrode;
at least one second capacitor dielectric structure located on the first capacitor dielectric structure, wherein the at least one second capacitor dielectric structure comprises a second conductive layer located on the first capacitor dielectric layer and a second capacitor dielectric layer located on the second conductive layer, the second conductive layer comprises a second left electrode and a second right electrode isolated from each other, the second left electrode is electrically connected to the first left electrode through the first left openings, the second right electrode is electrically connected to the first right electrode through the first right openings, the second capacitor dielectric layer comprises second left openings located above the second left electrode and second right openings located above the second right electrode, the second left openings and the first left openings are offset from each other, and the second right openings and the first right openings are offset from each other;
a third conductive layer located on the at least one second capacitor dielectric structure, wherein the third conductive layer comprises a third left electrode and a third right electrode isolated from each other, the third left electrode is electrically connected to the second left electrode through the second left openings, and the third right electrode is electrically connected to the second right electrode through the second right openings;
a third interlayer dielectric layer located on the third conductive layer;
a first bonding pad and a second bonding pad respectively located on the third interlayer dielectric layer; and
first metal pillars and second metal pillars respectively formed in the third interlayer dielectric layer, wherein the third left electrode is electrically connected to the first bonding pad by the first metal pillars, and the third right electrode is electrically connected to the second bonding pad by the second metal pillars.

5. A capacitor unit, comprising:
a substrate;
an isolation layer located on the substrate;
a capacitor stacked structure located on the isolation layer, wherein the isolation layer electrically isolates the substrate from the capacitor stacked structure; and
two electrode connectors located on the capacitor stacked structure and being exposed, wherein
the capacitor stacked structure comprises:
a first capacitor dielectric structure located on the isolation layer and having a first conductive layer located on the isolation layer and a first capacitor dielectric layer located on the first conductive layer, wherein the first conductive layer comprises a first left electrode and a first right electrode isolated from each other, and the first

Assignees

• Powerchip Semiconductor Mfg Corp

Inventors

• Lin Wei-Yu
• Cheng Shih-Hao

Classifications

• H10D1/716

  having vertical extensions · CPC title

• H10D1/696 Primary

  comprising multiple layers, e.g. comprising a barrier layer and a metal layer (barrier layers to prevent diffusion of hydrogen or oxygen in perovskite based capacitors H10D1/688) · CPC title

• H10D1/043

  using patterning processes to form electrode extensions, e.g. etching · CPC title

• H10D1/042

  using deposition processes to form electrode extensions · CPC title

• H01G4/306 Primary

  made by thin film techniques · CPC title