Pixel circuit, driving method thereof and display device

Patent metadata

Field	Value
Publication number	US-11620942-B2
Application number	US-201816466418-A
Country	US
Kind code	B2
Filing date	Nov 21, 2018
Priority date	Jan 5, 2018
Publication date	Apr 4, 2023
Grant date	Apr 4, 2023

Abstract

A pixel circuit, a driving method thereof and a display device are provided. The pixel circuit includes a drive circuit, a data writing circuit, a compensation-and-reset circuit, and a storage circuit. The drive circuit includes a control terminal, a first terminal and a second terminal, and is configured to control a driving current for driving a light-emitting element to emit light; the data writing circuit is configured to write a data signal to the control terminal of the drive circuit in response to a scanning signal; the compensation-and-reset circuit is configured to apply the reset voltage to the control terminal of the drive circuit in response to a compensation signal; the storage circuit is configured to store the data signal that is wrote and a threshold voltage, and to couple and adjust a voltage of the control terminal of the drive circuit.

First claim

What is claimed is:

1. A pixel circuit, comprising a drive circuit, a data writing circuit, a compensation-and-reset circuit, a light-emitting control circuit, and a storage circuit,
wherein the drive circuit comprises a control terminal, a first terminal and a second terminal, and is configured to control a driving current for driving a light-emitting element to emit light;
the data writing circuit is connected to the control terminal of the drive circuit and configured to write a data signal to the control terminal of the drive circuit in response to a scanning signal;
the compensation-and-reset circuit is connected to the control terminal of the drive circuit and a reset voltage terminal, and is configured to electrically connect the control terminal of the drive circuit and the second terminal of the drive circuit and apply a reset voltage to the control terminal of the drive circuit in response to a compensation signal; and
the storage circuit is configured to store the data signal that is wrote and a threshold voltage, and to couple and adjust a voltage of the control terminal of the drive circuit,
wherein the storage circuit comprises a first storage circuit and a second storage circuit;
the first storage circuit is connected to the control terminal of the drive circuit and the first terminal of the drive circuit, and configured to store the data signal that is wrote;
the second storage circuit is connected to a first voltage terminal and the first terminal of the drive circuit, and is configured to couple and adjust the voltage of the control terminal of the drive circuit;
the first storage circuit comprises a first storage capacitor, and the second storage circuit comprises a second storage capacitor;
a capacitance value of the second storage capacitor is larger than a capacitance value of the first storage capacitor, and a value of a driving current I OLED flowing through the light-emitting element is obtained according to a following formula:
I OLED ≈½ *K *( V data− V ref) 2 ,

where K=W*Cox*U/L, Vref represents a reset voltage, and Vdata represents a voltage of the data signal;
the compensation-and-reset circuit comprises a compensation sub-circuit and a reset sub-circuit, wherein
the compensation sub-circuit comprises a control terminal, a first terminal and a second terminal, which are respectively connected to the compensation signal terminal, a first node and a third node, and
the reset sub-circuit comprises a control terminal, a first terminal and a second terminal, which are respectively connected to the compensation signal terminal, the reset voltage terminal and the first node; and
the light-emitting control circuit comprises a control terminal, a first terminal, and a second terminal, which are connected to a light-emitting control line, the first voltage terminal, and the first terminal of the drive circuit, respectively, and configured to apply a first voltage to the first terminal of the drive circuit in response to a light-emitting control signal,
wherein during a display period of the pixel circuit, the light-emitting control signal holds an inactive level at a reset and compensation stage and a data writing stage and holds an active level at a light-emitting stage and a stage subsequent to the light-emitting stage, the compensation signal holds an active level at the reset and compensation stage and holds an inactive level at other stages, and the scanning signal holds an active level at the data writing stage and holds an inactive level at other stages.

2. The pixel circuit according to claim 1 , wherein the control terminal of the drive circuit is connected to the first node, the first terminal of the drive circuit is connected to a second node, and the second terminal of the drive circuit is connected to the third node;
the data writing circuit comprises a control terminal, a first terminal and a second terminal, which are respectively connected to a scanning line, a data line and the first node;
the compensation-and-reset circuit is connected to a compensation signal terminal, the reset voltage terminal, the first node and the third node; and
the light-emitting element is connected to the third node and a second voltage terminal.

3. The pixel circuit according to claim 2 , wherein the drive circuit comprises a first transistor;
a gate electrode of the first transistor is connected to the first node and serves as the control terminal of the drive circuit, a first electrode of the first transistor is connected to the second node and serves as the first terminal of the drive circuit, and a second electrode of the first transistor is connected to the third node and serves as the second terminal of the drive circuit.

4. The pixel circuit according to claim 2 , wherein the data writing circuit comprises a second transistor;
a gate electrode of the second transistor, as the control terminal of the data writing circuit, is configured to be connected to the scanning line to receive the scanning signal, a first electrode of the second transistor, as the first terminal of the data writing circuit, is configured to be connected to the data line to receive the data signal, and a second electrode of the second transistor, as the second terminal of the data writing circuit, is connected to the first node.

5. The pixel circuit according to claim 1 , wherein the compensation sub-circuit comprises a third transistor;
a gate electrode of the third transistor is configured to be connected to the compensation signal terminal to receive the compensation signal and serves as the control terminal of the compensation sub-circuit,
a first electrode of the third transistor is connected to the first node and serves as the first terminal of the compensation sub-circuit, and
a second electrode of the third transistor is connected to the third node and serves as the second terminal of the compensation sub-circuit.

6. The pixel circuit according to claim 2 , wherein
a first electrode of the first storage capacitor is connected to the first node, and a second electrode of the first storage capacitor is connected to the second node.

7. The pixel circuit according to claim 2 , wherein
a first electrode of the second storage capacitor is configured to be connected to the first voltage terminal to receive a first voltage, and a second electrode of the second storage capacitor is connected to the second node.

8. The pixel circuit according to claim 1 , wherein the reset sub-circuit comprises a fourth transistor;
a gate electrode of the fourth transistor is configured to be connected to the compensation signal terminal to receive the compensation signal and serves as the control terminal of the reset sub-circuit,
a first electrode of the fourth transistor is configured and connected to the reset voltage terminal to receive the reset voltage and serves as the first terminal of the reset sub-circuit, and
a second electrode of the fourth transistor is connected to the first node and serves as the second terminal of the reset sub-circuit.

9. The pixel circuit according to claim 2 , wherein the light-emitting control circuit comprises a fifth transistor;
a gate electrode of the fifth transistor, as the control terminal of the light-emitting control circuit, is configured to be connected to the light-emitting control line to receive the light-emitting control signal,
a first electrode of the fifth transistor, as the first terminal of the light-emitting control circuit, is configured to be connected to the first voltage terminal to receive the first voltage, and
a second electrode of the fifth transistor, as the second terminal of the light-emitting control circuit, is connected to the second node.

Assignees

• Boe Technology Group Co Ltd

Inventors

• Yang Chengchung
• Gao Xueling
• Peng Kuanjun

Classifications

• G09G2300/0819

  used for counteracting undesired variations, e.g. feedback or autozeroing · CPC title

• G09G2300/0852

  being a dynamic memory with more than one capacitor · CPC title

• G09G3/3233 Primary

  with pixel circuitry controlling the current through the light-emitting element · CPC title

• G09G2300/0861

  with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title

• G09G2320/0233

  Improving the luminance or brightness uniformity across the screen · CPC title