Computing device and method

Patent metadata

Field	Value
Publication number	US-11620130-B2
Application number	US-201916715009-A
Country	US
Kind code	B2
Filing date	Dec 16, 2019
Priority date	Feb 13, 2018
Publication date	Apr 4, 2023
Grant date	Apr 4, 2023

Abstract

The present disclosure provides a computation device. The computation device is configured to perform a machine learning computation, and includes an operation unit, a controller unit, and a conversion unit. The storage unit is configured to obtain input data and a computation instruction. The controller unit is configured to extract and parse the computation instruction from the storage unit to obtain one or more operation instructions, and to send the one or more operation instructions and the input data to the operation unit. The operation unit is configured to perform operations on the input data according to one or more operation instructions to obtain a computation result of the computation instruction. In the examples of the present disclosure, the input data involved in machine learning computations is represented by fixed-point data, thereby improving the processing speed and efficiency of training operations.

First claim

What is claimed is:

1. A computation device, comprising:
a storage unit,
a conversion unit,
an operation unit, and
a controller unit;
wherein the storage unit comprises a cache and a register; wherein:
the controller unit is configured to determine a decimal point position of first input data and a bit width of fixed-point data, wherein the bit width of the fixed-point data is the bit width of the first input data converted into the fixed-point data;
the operation unit is configured to initialize the decimal point position of the first input data and adjust the decimal point position of the first input data; and store the adjusted decimal point position of the first input data in the cache of the storage unit;
the controller unit is configured to obtain the first input data and a plurality of operation instructions from the register, and obtain the adjusted decimal point position of the first input data and the first input data from the cache; and transmit the adjusted decimal point position of the first input data and the first input data to the conversion unit;
the conversion unit is configured to convert the first input data into a second input data according to the adjusted decimal point position of the first input data;
and wherein the initializing the decimal point position of the first input data by the operation unit includes: initializing the decimal point position of the first input data according to a maximum absolute value of the first input data.

2. The computation device of claim 1 , wherein initializing the decimal point position of the first input data according to the maximum absolute value of the first input data by the operation unit includes:
the operation unit initializes the decimal point position of the first input data according to a first preset formula and the maximum absolute value of the first input data,
wherein the preset first formula is s a =┌log 2 a max −bitnum+1┐, the s a represents the initialized decimal point position of the first input data, the a max represents the maximum absolute value of the first input data, and the bitnum represents the bit width of the fixed-point data converted from the first input data.

3. The computation device of claim 1 , wherein adjusting the decimal point position of the first input data by the operation unit includes:
adjusting the decimal point position of the first input data upwardly by a single step according to the maximum absolute value of the first input data, or
adjusting the decimal point position of the first input data upwardly step by step according to the maximum absolute value of the first input data, or
adjusting the decimal point position of the first input data upwardly by a single step according to the first input data distribution, or
adjusting the decimal point position of the first input data upwardly step by step according to the first input data distribution, or
adjusting the decimal point position of the first input data downwardly according to the absolute value of the first input data.

4. The computation device of claim 1 , wherein the computation device is configured to execute a machine learning computation, and wherein:
the controller unit is further configured to transmit the plurality of operation instructions to the operation unit,
the conversion unit is further configured to transmit the second input data to the operation unit, and
the operation unit is further configured to perform operations on the second input data according to the plurality of operation instructions to obtain an operation result.

5. The computation device of claim 4 , wherein the machine learning computation includes an artificial neural network operation, the first input data includes an input neuron and a weight, and the computation result is an output neuron.

6. The computation device of claim 4 , wherein the operation unit includes a primary processing circuit and a plurality of secondary processing circuits, wherein:
the primary processing circuit is configured to perform pre-processing on the second input data and to transmit data and the plurality of operation instructions between the plurality of secondary processing circuits and the primary processing circuit,
the plurality of secondary processing circuits is configured to perform an intermediate operation to obtain a plurality of intermediate results according to the second input data and the plurality of operation instructions transmitted from the primary processing circuit, and to transmit the plurality of intermediate results to the primary processing circuit, and
the primary processing circuit is further configured to perform post-processing on the plurality of intermediate results to obtain the computation result of the computation instruction.

7. The computation device of claim 6 , further comprising a storage unit and a direct memory access (DMA) unit, wherein:
the storage unit includes any combination of a register and a cache, wherein the cache includes a scratch pad cache and is configured to store the first input data, and the register is configured to store scalar data in the first input data, and
the DMA unit is configured to read data from the storage unit or store data in the storage unit.

8. The computation device of claim 1 , wherein when the first input data is fixed-point data, the operation unit further includes:
a derivation unit configured to derive a decimal point position of at least one intermediate result according to the decimal point position of the first input data, wherein the at least one intermediate result is obtained by operating according to the first input data.

9. The computation device of claim 8 , wherein the operation unit further includes:
a data cache unit configured to cache the at least one intermediate result.

10. The computation device of claim 4 , wherein the operation unit includes a tree module; wherein:
the tree module includes a root port coupled with the primary processing circuit and a plurality of branch ports coupled with the plurality of secondary processing circuits, and
the tree module is configured to forward data and the plurality of operation instructions transmitted among the primary processing circuit and the plurality of secondary processing circuits;
and wherein the tree module is an n-tree structure, the n being an integer greater than or equal to two.

11. The computation device of claim 4 , wherein the operation unit further includes a branch processing circuit; wherein:
the primary processing circuit is configured to:
determine that the input neurons are broadcast data and the weights are distribution data,
divide the distribution data into a plurality of data blocks, and
transmit at least one of the plurality of data blocks, the broadcast data, and at least one of the plurality of operation instructions to the branch processing circuit;

and wherein the branch processing circuit is configured to forward the data blocks, the broadcast data, and the plurality of operation instructions transmitted among the primary processing circuit and the plurality of secondary processing circuits,
the plurality of secondary processing circuits is configured to perform operations on the data blocks received and the broadcast data received according to the plurality of operation instructions to obtain a plurality of intermediate results, and to transmit the plurality of intermediate results to the branch processing circuit, and
the primary processing circuit is further configured to perform post-processing on the plurality of intermediate results received from the branch processing circuit to obtain a computation result of the computation instruction, and to send t

Assignees

• Shanghai Cambricon Inf Tech Co Ltd

Inventors

• Zhang Yao
• Wang Bingrui

Classifications

• G06N3/08

  Learning methods · CPC title

• G06N3/0495

  Quantised networks; Sparse networks; Compressed networks · CPC title

• G06N3/0464

  Convolutional networks [CNN, ConvNet] · CPC title

• G06F9/30036

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title

• G06F7/491

  Computations with decimal numbers {radix 12 or 20. (G06F7/4824 takes precedence)} · CPC title