Converting a boolean masked value to an arithmetically masked value for cryptographic operations

Patent metadata

Field	Value
Publication number	US-11620109-B2
Application number	US-202017124374-A
Country	US
Kind code	B2
Filing date	Dec 16, 2020
Priority date	Mar 3, 2016
Publication date	Apr 4, 2023
Grant date	Apr 4, 2023

Abstract

A first input share value, a second input share value, and a third input share value may be received. The first input share value may be converted to a summation or subtraction between an input value and a combination of the second input share value and the third input share value. A random number value may be generated and combined with the second input share value and the third input share value to generate a combined value. Furthermore, a first output share value may be generated based on a combination of the converted first input share value, the combined value, and additional random number values.

First claim

What is claimed is:

1. A system comprising:
a set of registers to store a first input share value, a second input share value, a third input share value, and a first output share value, wherein the first input share value represents a Boolean combination between an input value, the second input share value, and the third input share value;
a first circuit to perform a cryptographic operation based on a Boolean operation and an arithmetic operation; and
a second circuit coupled to the set of registers and the first circuit, wherein the second circuit is to:
convert the first input share value to a summation or subtraction between the input value and a combination of the second input share value and the third input share value;
generate a first random value;
combine the first random value with the second input share value and the third input share value to generate a combined value;
convert the combined value to a summation or subtraction between the first random value and a combination of the second input share value and the third input share value;
generate a second random value; and
generate the first output share value based on a combination of the converted first input share value, the converted combined value, and the second random value.

2. The system of claim 1 , wherein the second circuit is further to:
receive an indication that the cryptographic operation being performed by the first circuit has switched from using the Boolean operation to using the arithmetic operation; and
in response to the indication, receive the first input share value, the second input share value, the third input share value from the set of registers.

3. The system of claim 1 , wherein the set of registers is further to store a second output share value and a third output share value, wherein the first output share value represents an arithmetic combination between the input value, the second output share value, and the third output share value, wherein the second random value corresponds to the second output share value, wherein the second circuit is further to generate a third random value, wherein the third random value corresponds to the third output share value.

4. The system of claim 3 , wherein the second output share value and the third output share value are the same as the second input share value and the third input share value.

5. The system of claim 3 , wherein the second output share value and the third output share value are each different than the second input share value and the third input share value.

6. The system of claim 1 , wherein the second circuit is further to:
receive at least one additional input share value, wherein the second circuit is to generate the first output share value further based on the at least one additional input share value.

7. The system of claim 1 , wherein to combine the first random value with the second input share value and the third input share value to generate the combined value, the second circuit is further to:
at a first time, perform an XOR operation between the first random value and the second input share value to generate an intermediate value;
at a second time after the first time, perform the XOR operation between the intermediate value and the third input share value to generate a second intermediate value; and
convert the second intermediate value to the combined value.

8. The system of claim 1 , wherein to generate the first output share value, the second circuit is further to:
perform a summation or subtraction between the converted first input share value and at least the second random value; and
perform a subtraction operation between a result of the summation or subtraction and the combined value.

9. A method comprising:
performing a cryptographic operation with a Boolean operation;
receiving a first input share value, a second input share value, and a third input share value;
converting the first input share value to a summation or subtraction between an input value and a combination of the second input share value and the third input share value;
generating a first random value;
combining the first random value with the second input share value and the third input share value to generate a combined value;
converting the combined value to a summation or subtraction between the first random value and a combination of the second input share value and the third input share value;
generating a second random value;
generating a first output share value based on a combination of the converted first input share value, the converted combined value, and the second random value; and
performing the cryptographic operation with an arithmetic operation by using the first output share value.

10. The method of claim 9 , further comprising:
receiving an indication that the cryptographic operation has switched from using the Boolean operation to using the arithmetic operation.

11. The method of claim 9 , wherein combining the first random value with the second input share value and the third input share value to generate the combined value comprises:
at a first time, performing an XOR operation between the first random value and the second input share value to generate an intermediate value;
at a second time after the first time, performing the XOR operation between the intermediate value and the third input share value to generate a second intermediate value; and
converting the second intermediate value to the combined value.

12. The method of claim 9 , wherein a second output share value and a third output share value associated with the first output share value are the same as the second input share value and the third input share value.

13. The method of claim 9 , wherein a second output share value and a third output share value associated with the first output share value are each different than the second input share value and the third input share value.

14. The method of claim 9 , further comprising:
receiving at least one additional input share value, wherein generating of the first output share value is further based on the at least one additional input share value.

15. The method of claim 9 , wherein combining the first random value with the second input share value and the third input share value to generate the combined value comprises:
at a first time, performing an XOR operation between the first random value and the second input share value to generate an intermediate value;
at a second time after the first time, performing the XOR operation between the intermediate value, the third input share value, and an additional random value to generate a second intermediate value; and
converting the second intermediate value to the combined value.

16. The method of claim 9 , wherein generating the first output share value comprises:
performing a summation or subtraction between the converted first input share value and the second random value and a third random value; and
performing a subtraction operation between a result of the summation or subtraction and the combined value.

17. A non-transitory computer readable medium including data that, when accessed by a processing device, cause the processing device to perform operations comprising:
performing a cryptographic operation with a Boolean operation;
receiving a first input share value, a second input share value, and a third input share value;
converting the first input share value to a summation or subtraction between an input value and a combination of the second input share value and the third input share value;
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Assignees

• Cryptography Res Inc

Inventors

• Hutter Michael
• Tunstall Michael

Classifications

• G06F7/58

  Random or pseudo-random number generators · CPC title

• H04L9/30

  Public key, i.e. encryption algorithm being computationally infeasible to invert or user's encryption keys not requiring secrecy · CPC title

• G06F2207/7233

  Masking, e.g. (A**e)+r mod n · CPC title

• H04L9/002

  Countermeasures against attacks on cryptographic mechanisms (network architectures or network communication protocols for protection against malicious traffic H04L63/1441) · CPC title

• G06F21/72

  in cryptographic circuits · CPC title