Biasing scheme for power amplifiers

Patent metadata

Field	Value
Publication number	US-11619958-B2
Application number	US-202117494665-A
Country	US
Kind code	B2
Filing date	Oct 5, 2021
Priority date	Feb 26, 2019
Publication date	Apr 4, 2023
Grant date	Apr 4, 2023

Abstract

A front-end module comprises a bias network including a current mirror, a junction temperature sensor, an n-bit analog-to-digital converter, an n-bit current source bank configured to automatically set reference current levels for one or more operating temperature regions, and a power amplifier. The bias network, junction temperature sensor, n-bit analog-to-digital converter, n-bit current source bank, and power amplifier are integrated on a first semiconductor die.

First claim

What is claimed is:

1. A biasing method for a power amplifier, the method comprising:
detecting a junction temperature of the power amplifier;
generating an output voltage based at least in part on the detected junction temperature;
converting the output voltage into digital bits; and
automatically setting reference current levels for one or more operating temperature regions based at least in part on the digital bits.

2. The method of claim 1 wherein the output voltage is configured to increase with increased junction temperature.

3. The method of claim 1 further comprising activating a circuit path in response to the junction temperature exceeding a threshold value.

4. The method of claim 1 wherein the output voltage is converted into n digital bits, and wherein the method further comprises setting reference current levels for 2 n +2 temperature regions.

5. The method of claim 1 wherein:
the junction temperature is detected at a junction temperature sensor;
the output voltage is converted into digital bits at an analog-to-digital converter;
the reference current levels are automatically set at a current source bank; and
the junction temperature sensor, analog-to-digital converter, and current source bank integrated on a first semiconductor die.

6. The method of claim 5 wherein the first semiconductor die further comprises the power amplifier.

7. The method of claim 5 wherein the first semiconductor die further comprises a bias network including a current mirror.

8. The method of claim 1 wherein the reference current levels are set without feedback loops.

9. A semiconductor die comprising:
a power amplifier;
a junction temperature sensor configured to detect a junction temperature of the power amplifier and convert the junction temperature to an output voltage;
an n-bit analog-to-digital converter configured to convert the output voltage into digital bits; and
an n-bit current source bank configured to automatically set reference current levels for one or more operating temperature regions.

10. The semiconductor die of claim 9 wherein the output voltage is configured to increase with increased junction temperature.

11. The semiconductor die of claim 9 wherein the n-bit analog-to-digital converter is configured to convert the output voltage into n digital bits, and wherein the n-bit current source bank is configured to automatically set reference current levels for 2 n +2 temperature regions.

12. The semiconductor die of claim 9 wherein the n-bit current source bank is configured to set reference current levels without feedback loops.

13. The semiconductor die of claim 9 further comprising a bias network including a current mirror.

14. The semiconductor die of claim 9 wherein the power amplifier is configured to provide an output power of at least 22 dBm.

15. A front-end module comprising:
a power amplifier;
a junction temperature sensor configured to detect a junction temperature of the power amplifier and convert the junction temperature to an output voltage;
an n-bit analog-to-digital converter configured to convert the output voltage into digital bits; and
an n-bit current source bank configured to automatically set reference current levels for one or more operating temperature regions.

16. The front-end module of claim 15 wherein the output voltage is configured to increase with increased junction temperature.

17. The front-end module of claim 15 wherein the n-bit analog-to-digital converter is configured to convert the output voltage into n digital bits, and wherein the n-bit current source bank is configured to automatically set reference current levels for 2 n +2 temperature regions.

18. The front-end module of claim 15 wherein the n-bit current source bank is configured to set reference current levels without feedback loops.

19. The front-end module of claim 15 wherein the junction temperature sensor, n-bit analog-to-digital converter, n-bit current source bank, and power amplifier are integrated on a first semiconductor die.

20. The front-end module of claim 15 further comprising a bias network including a current mirror.

Assignees

• Skyworks Solutions Inc

Inventors

• LIANG Bang Li

Classifications

• G05F3/30

  Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities (G05F3/26 takes precedence) · CPC title

• G05F3/225 Primary

  producing a current or voltage as a predetermined function of the temperature · CPC title

• G05F1/461

  using an operational amplifier as final control device · CPC title

• G05F1/565 Primary

  sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor (G05F1/563 takes precedence) · CPC title

• G05F1/468

  characterised by reference voltage circuitry, e.g. soft start, remote shutdown · CPC title