Remote mapping of circuit speed variation due to process, voltage and temperature using a network of digital sensors

US11616841B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11616841-B2
Application numberUS-202016784482-A
CountryUS
Kind codeB2
Filing dateFeb 7, 2020
Priority dateFeb 7, 2020
Publication dateMar 28, 2023
Grant dateMar 28, 2023

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A digital sensor network is overlaid on an integrated circuit for identifying and mapping hotspots in the integrated circuit. The digital sensor network may include a plurality of digital sensors distributed within an area of an integrated circuit component of an integrated circuit. Each of the plurality of digital sensors may include a ring oscillator and may be configured to output a counter value of a ring oscillator counted over a designated period. A sensor network control unit may be provided that is communicatively connected to the plurality of digital sensors via a communication circuit. The sensor network control unit may be configured to receive a plurality of counter values including the counter value from each of the plurality of digital sensors and identify a hotspot within the area of the integrated circuit.

First claim

Opening claim text (preview).

What is claimed is: 1. A digital sensor network, comprising: a plurality of digital sensors distributed within an area of an integrated circuit component of an integrated circuit, wherein each of the plurality of digital sensors is configured to output a counter value counted over a designated period; and a sensor network control unit communicatively connected to the plurality of digital sensors via a communication circuit, wherein the sensor network control unit is configured to: receive a plurality of counter values including the counter value from each of the plurality of digital sensors; sort the plurality of counter values associated with each of a plurality of perimeter digital sensors of a critical tile surrounding a critical digital sensor of the critical tile, wherein the plurality of digital sensors includes the plurality of perimeter digital sensors; determine a subset of potential hotspots within the area of the integrated circuit component based on potential hotspots within a half tile width diameter around the critical digital sensor and relationships of the sorted plurality of counter values indicating relationships between each of the plurality of perimeter digital sensors; and identify a hotspot within the area of the integrated circuit component. 2. The digital sensor network of claim 1 , wherein the sensor network control unit comprises a critical digital sensor data selection unit configured to: compare the plurality of counter values; identify a counter value of a comparison of the plurality of counter values as a critical counter value; and identify the critical digital sensor associated with the critical counter value. 3. The digital sensor network of claim 2 , wherein the critical digital sensor data selection unit is configured such that comparing the plurality of counter values comprises adjusting a counter value of the plurality of counter values from a digital sensor of the plurality of digital sensors using calibration coefficients for the digital sensor. 4. The digital sensor network of claim 1 , wherein the sensor network control unit comprises a tile data selection unit configured to: identify the critical tile associated with the critical digital sensor, wherein the critical tile comprises a first group of the plurality of digital sensors with the critical digital sensor as a center digital sensor surrounded by the plurality of perimeter digital sensors; and identify the plurality of perimeter digital sensors. 5. The digital sensor network of claim 1 , wherein the sensor network control unit comprises an arithmetic unit configured to: sort the plurality of counter values associated with each of the plurality of perimeter digital sensors of the critical tile surrounding the critical digital sensor of the critical tile; and determine the subset of potential hotspots within the area of the integrated circuit component based the on potential hotspots within the half tile width diameter around the critical digital sensor and the relationships of the sorted plurality of counter values indicating the relationships between each of the plurality of perimeter digital sensors. 6. The digital sensor network of claim 5 , wherein the arithmetic unit is further configured to: determine a plurality of environmental conditions including an environmental condition at each potential hotspot of the subset of potential hotspots; and identify a most extreme environmental condition from the plurality of environmental conditions, wherein identifying a hotspot within the area of the integrated circuit component comprises identifying the hotspot as a potential hotspot having the most extreme environmental condition. 7. The digital sensor network of claim 5 , wherein the arithmetic unit is further configured to map the hotspot to a location of the hotspot in the critical tile using a location of a perimeter digital sensor of the plurality of perimeter digital sensors, wherein the perimeter digital sensor is associated with a top sorted counter value of the sorted plurality of counter values. 8. The digital sensor network of claim 1 , wherein the sensor network control unit comprises an integrated circuit position mapping unit configured to map the hotspot to a location in the integrated circuit using a location of the hotspot in the critical tile and a location of the critical tile in the integrated circuit. 9. The digital sensor network of claim 1 , wherein the sensor network control unit comprises an arithmetic unit configured to calculate calibration coefficients for a digital sensor of the plurality of digital sensors using a reference counter value of the digital sensor and a counter value from the digital sensor of the plurality of counter values, wherein the reference counter value is an expected counter value from the digital sensor while the integrated circuit component has a control factor applied and the counter value is a measured counter value from the digital sensor while the integrated circuit component has the control factor applied. 10. A digital sensor network, comprising: a plurality of digital sensors distributed within an area of an integrated circuit component of an integrated circuit, wherein each of the plurality of digital sensors includes a plurality of components electrically connected via a first communication circuit, including: a ring oscillator configured to output an oscillating ring oscillator signal; a high speed counter configured to output a counter value signal representing a counter value of the oscillating ring oscillator signal; and a counter storage configured to: store the counter value; and output a sensor output signal representing the stored counter value; and a sensor network control unit communicatively connected to the plurality of digital sensors via a second communication circuit, wherein the sensor network control unit is configured to: receive a plurality of sensor output signals including the sensor output signal from each of the plurality of digital sensors; sort the plurality of sensor output signals associated with each of a plurality of perimeter digital sensors of a critical tile surrounding a critical digital sensor of the critical tile, wherein the plurality of digital sensors includes the plurality of perimeter digital sensors; determine a subset of potential hotspots within the area of the integrated circuit component based on potential hotspots within a half tile width diameter around the critical digital sensor and relationships of the sorted plurality of counter values indicating relationships between each of the plurality of perimeter digital sensors; and identify a hotspot within the area of the integrated circuit component. 11. The digital sensor network of claim 10 , wherein: the ring oscillator is further configured to oscillate a ring oscillator signal in response to receiving a first edge of a trigger signal; each of the plurality of digital sensors includes the plurality of components electrically connected via the first communication circuit, further including a storage signal synchronizer configured to: receive the trigger signal; receive the ring oscillator signal; and output a clear counter signal in response to receiving a second edge of the trigger signal and an edge of the ring oscillator signal; and the counter storage is further configured to receive the clear counter signal wherein outputting a sensor output signal comprises outputting the sensor output signal in response to receiving the clear counter signal. 12. The digital sensor network of claim 10 , wherein the plurality of digital sensors distributed within the area of the integrated circuit

Assignees

Inventors

Classifications

  • Hotspot localization · CPC title

  • H04W84/18Primary

    Self-organising networks, e.g. ad-hoc networks or sensor networks · CPC title

  • G01D21/02Primary

    Measuring two or more variables by means not covered by a single other subclass · CPC title

  • Circuits therefor {, e.g. for generating test voltages, sensing circuits (G01R31/1209 - G01R31/1227 take precedence; for testing switches G01R31/327)} · CPC title

  • Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations (thermal management in cooling arrangements of a computing system G06F1/206) · CPC title

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What does patent US11616841B2 cover?
A digital sensor network is overlaid on an integrated circuit for identifying and mapping hotspots in the integrated circuit. The digital sensor network may include a plurality of digital sensors distributed within an area of an integrated circuit component of an integrated circuit. Each of the plurality of digital sensors may include a ring oscillator and may be configured to output a counter …
Who is the assignee on this patent?
Taiwan Semiconductor Mfg Co Ltd
What technology area does this patent fall under?
Primary CPC classification H04W84/18. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 28 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).