Echo canceller system and echo cancelling method

US11616530B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11616530-B2
Application numberUS-202117370049-A
CountryUS
Kind codeB2
Filing dateJul 8, 2021
Priority dateFeb 9, 2021
Publication dateMar 28, 2023
Grant dateMar 28, 2023

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Abstract

Official abstract text for this publication.

An echo canceller system includes a data transmitter circuit and an echo canceller circuit. The data transmitter circuit is configured to receive a transmitted signal. The echo canceller circuit includes a first filter. The first filter is configured to generate a first filtered signal according to the transmitted signal and a filter coefficient vector. The filter coefficient vector is updated according to a high-frequency leakage process. The echo canceller circuit is further configured to generate an echo cancelling signal according to the first filtered signal. The data transmitter circuit is further configured to generate an output signal according to a received signal and the echo cancelling signal.

First claim

Opening claim text (preview).

What is claimed is: 1. An echo canceller system, comprising: a data transmitter circuit configured to receive a transmitted signal; and an echo canceller circuit configured to generate an echo cancelling signal according to a first filtered signal and comprising: a first filter configured to generate the first filtered signal according to the transmitted signal and a filter coefficient vector; and a calculation circuit associated with an updating circuit to update the filter coefficient vector according to a current filter coefficient vector, a least significant bit (LSB) vector, and a high-frequency leakage vector, wherein the data transmitter circuit is further configured to generate an output signal according to a received signal and the echo cancelling signal. 2. The echo canceller system of claim 1 , wherein the first filter performs a convolution calculation according to the transmitted signal and the filter coefficient vector to generate the first filtered signal. 3. The echo canceller system of claim 1 , wherein the calculation circuit accumulates a coefficient accumulation vector according to an error value and a data vector corresponding to the transmitted signal, and subtracts the LSB vector from the coefficient accumulation vector when a tap of the coefficient accumulation vector is accumulated over a LSB. 4. The echo canceller system of claim 1 , wherein the filter coefficient vector comprises a plurality of taps, wherein the calculation circuit sets the high-frequency leakage vector to be equal to a product of a LSB, a leakage vector of the filter coefficient vector, and a sign of a high-frequency component parameter when an absolute value of the high-frequency component parameter is greater than or equal to an absolute value of a product of the LSB and a total number of the taps. 5. The echo canceller system of claim 4 , wherein the calculation circuit sets the high-frequency component parameter to be equal to a difference of a sum of a plurality of odd taps and a sum of a plurality of even taps. 6. The echo canceller system of claim 4 , wherein the calculation circuit sets the high-frequency leakage vector to be zero when the absolute value of the high-frequency component parameter is less than the absolute value of the product of the LSB and the total number of the taps. 7. The echo canceller system of claim 1 , wherein the calculation circuit associates with the updating circuit to update the high-frequency leakage vector is according to an updating period, the updating period corresponds to a plurality of candidate values and a decrease in a period length of the updating period corresponds to an increase in an updating speed. 8. The echo canceller system of claim 1 , wherein the echo canceller circuit further comprises: a second filter configured to generate a second filtered signal according to the transmitted signal; an adder configured to generate a digital signal according to the first filtered signal and a random sequence; a shaping circuit configured to generate a first shaping signal according to the digital signal and the second filtered signal; and a digital-to-analog converter configured to generate the echo cancelling signal according to the first shaping signal and a second shaping signal corresponding to the transmitted signal. 9. An echo cancelling method, comprising: receiving, by a data transmitter circuit, a transmitted signal; generating, by a first filter of an echo canceller circuit, a first filtered signal according to the transmitted signal and a filter coefficient vector; updating, by a calculation circuit and an updating circuit of the echo canceller circuit, the filter coefficient vector according to a current filter coefficient vector, a least significant bit (LSB) vector, and a high-frequency leakage vector; generating, by the echo canceller circuit, an echo cancelling signal according to the first filtered signal; and generating, by the data transmitter circuit, an output signal according to a received signal and the echo cancelling signal. 10. The echo cancelling method of claim 9 , further comprising: performing, by the first filter, a convolution calculation according to the transmitted signal and the filter coefficient vector to generate the first filtered signal. 11. The echo cancelling method of claim 9 , further comprising: accumulating, by the calculation circuit, a coefficient accumulation vector according to an error value and a data vector corresponding to the transmitted signal; and subtracting, by the calculation circuit, the LSB vector from the coefficient accumulation vector when a tap of the coefficient accumulation vector is accumulated over a LSB. 12. The echo cancelling method of claim 9 , wherein the filter coefficient vector comprises a plurality of taps and the echo cancelling method further comprises: setting, by the calculation circuit, the high-frequency leakage vector to be equal to a product of a LSB, a leakage vector of the filter coefficient vector, and a sign of a high-frequency component parameter when an absolute value of the high-frequency component parameter is greater than or equal to an absolute value of a product of the LSB and a total number of the taps. 13. The echo cancelling method of claim 12 , further comprising: setting, by the calculation circuit, the high-frequency component parameter to be equal to a difference of a sum of a plurality of odd taps and a sum of a plurality of even taps. 14. The echo cancelling method of claim 12 , further comprising: setting, by the calculation circuit, the high-frequency leakage vector to be zero when the absolute value of the high-frequency component parameter is less than the absolute value of the product of the LSB and the total number of the taps. 15. The echo cancelling method of claim 9 , further comprising: updating, by the calculation circuit and the updating circuit, the high-frequency leakage vector according to an updating period corresponding to a plurality of candidate values, wherein a decrease in a length of the updating period corresponds to an increase in an updating speed. 16. The echo cancelling method of claim 9 , further comprising: generating, by a second filter of the echo canceller circuit, a second filtered signal according to the transmitted signal; generating, by an adder of the echo canceller circuit, a digital signal according to the first filtered signal and a random sequence; generating, by a shaping circuit of the echo canceller circuit, a first shaping signal according to a digital signal and the second filtered signal; and generating, by a digital-to-analog converter of the echo canceller circuit, the echo cancelling signal according to the first shaping signal and a second shaping signal corresponding to the transmitted signal.

Assignees

Inventors

Classifications

  • H04B3/231Primary

    Echo cancellers using readout of a memory to provide the echo replica · CPC title

  • H04B1/04Primary

    Circuits · CPC title

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What does patent US11616530B2 cover?
An echo canceller system includes a data transmitter circuit and an echo canceller circuit. The data transmitter circuit is configured to receive a transmitted signal. The echo canceller circuit includes a first filter. The first filter is configured to generate a first filtered signal according to the transmitted signal and a filter coefficient vector. The filter coefficient vector is updated …
Who is the assignee on this patent?
Realtek Semiconductor Corp
What technology area does this patent fall under?
Primary CPC classification H04B3/231. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 28 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).