Thin film transistor and manufacturing method thereof, display substrate and display apparatus

Patent metadata

Field	Value
Publication number	US-11616147-B2
Application number	US-202017254851-A
Country	US
Kind code	B2
Filing date	Apr 8, 2020
Priority date	Apr 9, 2019
Publication date	Mar 28, 2023
Grant date	Mar 28, 2023

Abstract

The disclosure provides a thin film transistor, a manufacturing method thereof, a display substrate and a display apparatus. The thin film transistor comprises a base substrate, and an active layer disposed on the base substrate, and the active layer comprises a channel region, and a source contact region and a drain contact region respectively positioned at two sides of the channel region; and a portion of at least one of the source contact region and the drain contact region close to the channel region includes a plurality of first sub-grooves disposed at a side of the active layer proximal to the base substrate and a plurality of second sub-grooves disposed at a side of the active layer distal to the base substrate, and the plurality of first sub-grooves and the plurality of second sub-grooves being alternately disposed along a direction parallel to an extension of the channel region.

First claim

What is claimed is:

1. A thin film transistor, comprising:
a base substrate,
an active layer disposed on the base substrate, the active layer comprising a channel region, and a source contact region and a drain contact region respectively located at two sides of the channel region;
wherein a portion of at least one of the source contact region and the drain contact region close to the channel region comprises a plurality of first sub-grooves disposed at a side of the active layer proximal to the base substrate and a plurality of second sub-grooves disposed at a side of the active layer distal to the base substrate, and the plurality of first sub-grooves and the plurality of second sub-grooves are disposed alternately along a direction parallel to an extension of the channel region.

2. The thin film transistor of claim 1 , wherein the plurality of first sub-grooves and the plurality of second sub-grooves have a same depth.

3. The thin film transistor of claim 2 , further comprising an insulating layer provided between the active layer and the base substrate;
wherein the insulating layer is provided with a plurality of first grooves at a side of the insulating layer proximal to the active layer, the plurality of first grooves are provided in the insulating layer at positions corresponding to the at least one of the source contact region and the drain contact region of the active layer close to the channel region, the plurality of first grooves are in one-to-one correspondence with the plurality of second sub-grooves, and orthographic projections of the plurality of first grooves and the plurality of second sub-grooves on the base substrate are overlapped, respectively.

4. The thin film transistor of claim 1 , further comprising an insulating layer provided between the active layer and the base substrate;
wherein the insulating layer is provided with a plurality of first grooves at a side of the insulating layer proximal to the active layer, the plurality of first grooves are provided in the insulating layer at positions corresponding to the at least one of the source contact region and the drain contact region of the active layer close to the channel region, the plurality of first grooves are in one-to-one correspondence with the plurality of second sub-grooves, and orthographic projections of the plurality of first grooves and the plurality of second sub-grooves on the base substrate are overlapped, respectively.

5. The thin film transistor of claim 4 , further comprising a light-shielding layer disposed between the base substrate and the insulating layer.

6. The thin film transistor of claim 5 , wherein the light-shielding layer is provided with a plurality of second grooves at a side of the light-shielding layer proximal to the insulating layer, the plurality of second grooves are provided in the light-shielding layer at positions corresponding to the at least one of the source contact region and the drain contact region of the active layer close to the channel region, the plurality of second grooves are in one-to-one correspondence with the plurality of second sub-grooves, and orthographic projections of the plurality of second grooves and the plurality of second sub-grooves on the base substrate are overlapped, respectively.

7. The thin film transistor of claim 6 , wherein the plurality of second grooves penetrate through the light-shielding layer.

8. The thin film transistor of claim 5 , wherein a material of the light-shielding layer comprises aluminum, molybdenum, or copper.

9. The thin film transistor of claim 1 , further comprising a gate insulating layer, a gate, and a source and a drain sequentially disposed on the active layer.

10. A method for manufacturing a thin film transistor, comprising:
forming a base substrate, and forming an active layer on the base substrate such that the active layer comprises a channel region, and a source contact region and a drain contact region respectively located at two sides of the channel region; and
forming a plurality of first sub-grooves at a side of the active layer proximal to the base substrate and a plurality of second sub-grooves at a side of the active layer distal to the base substrate at a portion of at least one of the source contact region and the drain contact region of the active layer close to the channel region such that the plurality of first sub-grooves and the plurality of second sub-grooves are disposed alternately along a direction parallel to an extension of the channel region.

11. The method of claim 10 , wherein the plurality of first sub-grooves and the plurality of second sub-grooves have a same depth.

12. The method of claim 11 , wherein before the forming the active layer on the base substrate, the method further comprises:
forming an insulating layer on the base substrate, and forming a plurality of first grooves on a side of the insulating layer proximal to the active layer at positions corresponding to the portion of the at least one of the source contact region and the drain contact region of the active layer close to the channel region; and
forming the active layer on the base substrate on which the insulating layer is formed such that the plurality of first grooves are in one-to-one correspondence with the plurality of second sub-grooves, and orthographic projections of the plurality of first grooves and the plurality of second sub-grooves on the base substrate are overlapped, respectively.

13. The method of claim 10 , wherein before the forming the active layer on the base substrate, the method further comprises:
forming an insulating layer on the base substrate, and forming a plurality of first grooves on a side of the insulating layer proximal to the active layer at positions corresponding to the portion of the at least one of the source contact region and the drain contact region of the active layer close to the channel region; and
forming the active layer on the base substrate on which the insulating layer is formed such that the plurality of first grooves are in one-to-one correspondence with the plurality of second sub-grooves, and orthographic projections of the plurality of first grooves and the plurality of second sub-grooves on the base substrate are overlapped, respectively.

14. The method of claim 13 , wherein before the forming the insulating layer on the base substrate, the method further comprises forming a light-shielding layer on the base substrate.

15. The method of claim 14 , wherein the forming the light-shielding layer on the base substrate comprises:
forming the light-shielding layer on a base substrate by a patterning process, and forming a plurality of second grooves on a side of the light-shielding layer proximal to the insulating layer at positions corresponding to the portion of the at least one of the source contact region and the drain contact region of the active layer close to the channel region such that the plurality of second grooves are in one-to-one correspondence with the plurality of second sub-grooves, and orthographic projections of the plurality of second grooves and the plurality of second sub-grooves on the base substrate are overlapped, respectively.

16. The method of claim 15 , wherein the plurality of second grooves penetrate through the light-shielding layer.

17. The method of claim 14 , wherein a material of the light-shielding layer comprises aluminum, molybdenum, or copper.

18. The method of claim 10 , further comprising forming a gate insulating layer on the active layer, and forming a gate, a source and a drain on the gate

Assignees

• Hefei Xinsheng Optoelectronics Technology Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Hu Yingbin
• Zhao Ce
• Ding Yuankui
• Song Wei
• Ni Liusong
• Sun Xuechao
• Hao Chaowei
• Yan Liangchen

Classifications

• H10P14/3434

  being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424) · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10D86/423

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

• H10D86/0221

  comprising manufacture, treatment or patterning of TFT semiconductor bodies · CPC title