Link evaluation for a memory device

Patent metadata

Field	Value
Publication number	US-11615862-B2
Application number	US-202017121314-A
Country	US
Kind code	B2
Filing date	Dec 14, 2020
Priority date	Dec 19, 2019
Publication date	Mar 28, 2023
Grant date	Mar 28, 2023

Abstract

Methods, systems, and devices for link evaluation for a memory device are described. A memory device may receive signaling over a channel and may identify logic values encoded into the signaling based on sampling the signaling against a reference voltage. The sampling may occur at a reference time within a sampling period. To evaluate a quality (e.g., margin of error) of the channel, the memory device may adjust the reference voltage, the reference time, or both, and either the memory device or the host device may determine whether the memory device is still able to correctly identify logic values encoded into signaling over the channel. In some cases, the channel quality may be evaluated during a refresh cycle or at another opportunistic time for the memory device.

First claim

What is claimed is:

1. A method, comprising:
receiving, at a memory device via a channel, first signaling associated with data to store at the memory device;
sampling the first signaling based at least in part on a first reference point within a time domain and a voltage domain to obtain the data, wherein the first reference point is at a first sampling time within a sample period;
receiving, at the memory device via the channel, second signaling associated with a sequence of logic values;
sampling the second signaling based at least in part on a second reference point within the time domain and the voltage domain to obtain a candidate sequence of logic values, wherein the second reference point is at a second sampling time within the sample period; and
transmitting, by the memory device, third signaling based at least in part on a comparison of the candidate sequence of logic values to the sequence of logic values.

2. The method of claim 1 , further comprising:
determining a match between the candidate sequence of logic values and the sequence of logic values; and
determining, based at least in part on the match, that a margin of error for the channel is greater than or equal to a difference between the second reference point and the first reference point.

3. The method of claim 1 , further comprising:
determining a mismatch between the candidate sequence of logic values and the sequence of logic values; and
determining, based at least in part on the mismatch, that a margin of error for the channel is less than a difference between the second reference point and the first reference point.

4. The method of claim 1 , further comprising:
identifying the second signaling as associated with the sequence of logic values based at least in part on a command received by the memory device.

5. The method of claim 4 , wherein identifying the second signaling as associated with the sequence of logic values is based at least in part on a timing relationship between the command being received and the second signaling being received.

6. The method of claim 4 , wherein the command comprises an auto refresh command.

7. The method of claim 1 , wherein the second reference point is earlier or later within time domain than the first reference point.

8. The method of claim 1 , wherein the second reference point is at a higher or lower voltage within the voltage domain than the first reference point.

9. The method of claim 1 , further comprising:
receiving, from a host device before receiving the second signaling, an indication of the sequence of logic values.

10. The method of claim 1 , further comprising:
sampling the second signaling based at least in part on the first reference point to obtain the sequence of logic values.

11. A method, comprising:
receiving, at a memory device via a channel, first signaling associated with data to store at the memory device;
sampling the first signaling based at least in part on a first reference point within a time domain and a voltage domain to obtain the data;
receiving, at the memory device via the channel, second signaling associated with a sequence of logic values;
sampling the second signaling based at least in part on a second reference point within the time domain and the voltage domain to obtain a candidate sequence of logic values and a third reference point in the time domain and the voltage domain to obtain a second candidate sequence of logic values; and
transmitting, by the memory device, third signaling based at least in part on a comparison of the candidate sequence of logic values to the sequence of logic values and a comparison of the second candidate sequence of logic values to the sequence of logic values.

12. The method of claim 11 , wherein sampling the second signaling based at least in part on the third reference point occurs after sampling the second signaling based at least in part on the second reference point.

13. The method of claim 11 , wherein sampling the second signaling based at least in part on the third reference point occurs concurrently with sampling the second signaling based at least in part on the second reference point.

14. The method of claim 1 , further comprising:
adjusting a time or voltage reference used by a sampler included in the memory device, wherein the adjusting is after sampling the first signaling and before sampling the second signaling, and wherein the second reference point corresponds to the adjusted time or voltage reference.

15. The method of claim 1 , further comprising:
activating a second sampler included in the memory device after sampling the first signaling, wherein a first sampler included in the memory device is operable to use the first reference point and the second sampler is operable to use the second reference point.

16. The method of claim 1 , wherein the third signaling comprises an indication of a margin of error for the channel, the method further comprising:
receiving, at the memory device, a command to calibrate a sampler for the channel.

17. The method of claim 1 , further comprising:
determining, based at least in part on the comparison, that a margin of error for the channel is deficient; and
calibrating a sampler based at least in part on determining that the margin of error is deficient, wherein the third signaling comprises an indication of the calibration.

18. A method, comprising:
transmitting, to a memory device via a channel, signaling associated with a sequence of logic values, wherein the signaling supports a determination of a condition of the channel;
receiving feedback from the memory device based at least in part on the signaling associated with the sequence of logic values, wherein the feedback is based on sampling the signaling based at least in part on a first reference point within a time domain and a voltage domain, and wherein the first reference point is at a first sampling time within a sample period; and
transmitting an instruction to the memory device based at least in part on the feedback.

19. The method of claim 18 , further comprising:
transmitting a command to the memory device that indicates the signaling is associated with the sequence of logic values.

20. The method of claim 18 , wherein the condition of the channel comprises a margin of error for the channel in at least one of a time domain or a voltage domain.

21. The method of claim 20 , wherein the feedback comprises an indication of whether the margin of error is below a threshold.

22. The method of claim 20 , wherein the feedback comprises an indication of a size of the margin of error, the method further comprising:
comparing the margin of error to a threshold.

23. The method of claim 18 , wherein the feedback comprises an indication of a candidate sequence of logic values determined by the memory device, the method further comprising:
comparing the candidate sequence of logic values to the sequence of logic values; and determining the condition of the channel based at least in part on the comparing.

24. An apparatus, comprising:
an array of memory cells operable to store data;
a channel operable to exchange data between the array of memory cells and a host device for the apparatus;
one or more samplers coupled with the channel and operable to determine logic values based at least in part on signals received via the channel, wherein at least one of the one or more samplers is operable to use a default r

Assignees

• Micron Technology Inc

Inventors

• Balb Markus
• Hein Thomas
• Hoenigschmid Heinz

Classifications

• G11C29/023 Primary

  in clock generator or timing circuitry · CPC title

• G11C29/50012 Primary

  of timing · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/061

  Improving I/O performance · CPC title

• H04L7/0008

  Synchronisation information channels, e.g. clock distribution lines · CPC title