Bypassing zero-value multiplications in a hardware multiplier

Patent metadata

Field	Value
Publication number	US-11614920-B2
Application number	US-202016869288-A
Country	US
Kind code	B2
Filing date	May 7, 2020
Priority date	May 7, 2020
Publication date	Mar 28, 2023
Grant date	Mar 28, 2023

Abstract

A device (e.g., integrated circuit chip) includes a first operand register, a second operand register, a multiplication unit, and a hardware logic component. The first operand register is configured to store a first operand value. The second operand register is configured to store a second operand value. The multiplication unit is configured to at least multiply the first operand value with the second operand value. The hardware logic component is configured to detect whether a zero value is provided and in response to a detection that the zero value is being provided: cause an update of at least the first operand register to be disabled, and cause a result of a multiplication of the first operand value with the second operand value to be a zero-value result.

First claim

What is claimed is:

1. A device, comprising:
a plurality of processing elements communicatively connected to one another and to a memory unit; and
the memory unit;
wherein a processing element of the plurality of processing elements comprises a control logic unit and a plurality of vector units, wherein:
the control logic unit is configured to control operation of the processing element, including by being configured to determine components of multiplication operands; and
each vector unit of the plurality of vector units comprises a vector multiply unit and is configured to utilize the vector multiply unit to compute a dot product result, and wherein the vector multiply unit comprises:
a first operand register configured to store a first operand value;
a second operand register configured to store a second operand value;
a multiplication unit configured to at least multiply the first operand value with the second operand value; and
a zero detector component configured to:
detect whether a zero value is provided;
in response to a detection at the same zero detector component that the zero value is being provided, disable updates to a plurality of operand registers configured to provide operands to the multiplication unit including the first operand register and the second operand register, wherein the first operation register and the second operand register are both directly connected to the same zero detector component configured to receive an input of the first operand value but not the second operand value and wherein the first operation register and the second operand register are not connected any other zero detector component besides the same zero detector component configured to receive the input of the first operand value but not the second operand value; and
in response to the detection that the zero value is being provided, cause a result of a multiplication of the first operand value with the second operand value to be a zero-value result.

2. The device of claim 1 , wherein the first operand value and the second operand value are in an integer number format.

3. The device of claim 1 , wherein the first operand value and the second operand value are in a floating-point number format.

4. The device of claim 1 , wherein the control logic unit is further configured to receive a multiply operation instruction that specifies an operand format type.

5. The device of claim 1 , wherein the zero detector component includes a comparator that is configured to detect whether the zero value is provided.

6. The device of claim 1 , wherein the zero detector component is configured to, in response to the detection that the zero value is being provided, cause an update of at least the first operand register to be disabled including by being configured to transmit a disable signal to the first operand register.

7. The device of claim 1 , wherein the zero detector component is further configured to, in response to the detection that the zero value is being provided, cause an update of the second operand register to be disabled.

8. The device of claim 7 , wherein the zero detector component is configured to, in response to the detection that the zero value is being provided, cause an update of the first operand register and the update of the second operand register to be disabled including by being configured to transmit disable signals to both the first operand register and the second operand register.

9. The device of claim 1 , wherein the zero detector component is configured to, in response to the detection that the zero value is being provided, cause the result of the multiplication of the first operand value with the second operand value to be the zero-value result including by being configured to transmit a signal indicating the detection that the zero value is being provided to an output logic component.

10. The device of claim 9 , wherein the output logic component is configured to select between an output of the multiplication unit and the zero-value result.

11. The device of claim 10 , wherein the output logic component is configured to select the zero-value result in response to the detection that the zero value is being provided.

12. The device of claim 11 , wherein the output logic component is configured to select the output of the multiplication unit in response to a detection by the zero detector component that a non-zero value is being provided.

13. The device of claim 1 , wherein the multiplication of the first operand value with the second operand value is a part of a plurality of multiplications associated with a vector multiplication or a dot product operation.

14. The device of claim 1 , wherein the multiplication of the first operand value with the second operand value is a part of a matrix operation.

15. The device of claim 1 , wherein the multiplication of the first operand value with the second operand value is a part of an artificial neural network operation.

16. A method, comprising:
communicatively connecting a plurality of processing elements to one another and to a memory unit, wherein a processing element of the plurality of processing elements comprises a control logic unit and a plurality of vector units, wherein:
the control logic unit is configured to control operation of the processing element, including by being configured to determine components of multiplication operands; and
each vector unit of the plurality of vector units comprises a vector multiply unit and is configured to utilize the vector multiply unit to compute a dot product result;

receiving a first operand value that is to be stored in a first operand register of the vector multiply unit;
receiving a second operand value that is to be stored in a second operand register of the vector multiply unit, wherein the first operand value and the second operand value are to be multiplied by a multiplication unit of the vector multiply unit;
detecting, with a zero detector component of the vector multiply unit, whether a zero value is provided; and
in response to a detection at the same zero detector component that the zero value is being provided:
disabling updates to a plurality of operand registers configured to provide operands to the multiplication unit including the first operand register and the second operand register, wherein the first operation register and the second operand register are both directly connected to the same zero detector component configured to receive an input of the first operand value but not the second operand value and wherein the first operation register and the second operand register are not connected any other zero detector component besides the same zero detector component configured to receive the input of the first operand value but not the second operand value; and
causing a result of a multiplication of the first operand value with the second operand value to be a zero-value result.

17. A device, comprising:
a matrix compute engine comprising a plurality of vector units, wherein each vector unit of the plurality of vector units comprises a vector multiply unit and is configured to utilize the vector multiply unit to compute a dot product result, wherein the vector multiply unit comprises:
a first operand register configured to store a first operand value;
a second operand register configured to store a second operand value;
a multiplication unit configured to at least multiply the first operand value with the second operand value; and
a zero detector component configured to:
detect whether a zero value is provided;
in response

Assignees

• Meta Platforms Inc

Inventors

• Ulrich Thomas Mark
• Diril Abdulkadir Utku
• Wang Zhao

Classifications

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F17/16 Primary

  Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)} · CPC title

• G06F7/523

  Multiplying only · CPC title

• G06N3/063

  using electronic means · CPC title

• G06F9/3001 Primary

  Arithmetic instructions · CPC title