Biasing scheme for power amplifiers

Patent metadata

Field	Value
Publication number	US-11614760-B2
Application number	US-202217668681-A
Country	US
Kind code	B2
Filing date	Feb 10, 2022
Priority date	Feb 26, 2019
Publication date	Mar 28, 2023
Grant date	Mar 28, 2023

Abstract

A front-end module comprises a low-dropout (LDO) voltage regulator, a reference current generator, and a power amplifier. The LDO voltage regulator, reference current generator, and power amplifier are integrated on a first semiconductor die.

First claim

What is claimed is:

1. A front-end module comprising:
a low-dropout (LDO) voltage regulator;
a power amplifier; and
a reference current generator directly connected to the LDO voltage regulator and the power amplifier, the reference current generator comprising a junction temperature sensor configured to detect a junction temperature value of the power amplifier and convert the junction temperature value to an output voltage value, an n-bit analog-to-digital converter configured to convert the output voltage value into digital bits, and a current source configured to generate discrete reference current levels for specific junction temperature regions based on the digital bits;
the LDO voltage regulator, reference current generator, and power amplifier being integrated on a first semiconductor die.

2. The front-end module of claim 1 further comprising a logic level slicer directly connected to the LDO voltage regulator and the reference current generator and configured to convert multiple logic levels to a single logic level.

3. The front-end module of claim 2 further comprising a logic decoder directly connected to an output of the logic level slicer and an output of the LDO voltage regulator.

4. The front-end module of claim 3 further comprising a level shifter directly connected to an output of the logic decoder.

5. The front-end module of claim 1 wherein the power amplifier comprises three or more field-effect transistors and wherein the power amplifier is configured to generate three or more different bias voltages.

6. The front-end module of claim 1 further comprising a mode detector integrated on the first semiconductor die.

7. The front-end module of claim 6 wherein the mode detector is configured to generate a power-down signal to power down the LDO voltage regulator.

8. The front-end module of claim 1 further comprising a voltage reference integrated on the first semiconductor die.

9. The front-end module of claim 8 wherein the voltage reference is configured to provide a reference voltage to the LDO voltage regulator and the reference current generator.

10. The front-end module of claim 1 wherein the power amplifier is configured to operate at a first level during transmit modes and operate at a second level during non-transmit modes.

11. A semiconductor die comprising:
a substrate;
a low-dropout (LDO) voltage regulator;
a power amplifier; and
a reference current generator directly connected to the LDO voltage regulator and the power amplifier, the reference current generator comprising a junction temperature sensor configured to detect a junction temperature value of the power amplifier and convert the junction temperature value to an output voltage value, an n-bit analog-to-digital converter configured to convert the output voltage value into digital bits, and a current source configured to generate discrete reference current levels for specific junction temperature regions based on the digital bits.

12. The semiconductor die of claim 11 further comprising a logic level slicer directly connected to the LDO voltage regulator and the reference current generator and configured to convert multiple logic levels to a single logic level.

13. The semiconductor die of claim 12 further comprising a logic decoder directly connected to an output of the logic level slicer and an output of the LDO voltage regulator.

14. The semiconductor die of claim 13 further comprising a level shifter directly connected to an output of the logic decoder.

15. The semiconductor die of claim 11 wherein the power amplifier comprises three or more field-effect transistors and wherein the power amplifier is configured to generate three or more different bias voltages.

16. The semiconductor die of claim 11 further comprising a mode detector.

17. The semiconductor die of claim 16 wherein the mode detector is configured to generate a power-down signal to power down the LDO voltage regulator.

18. The semiconductor die of claim 11 further comprising a voltage reference.

19. The semiconductor die of claim 18 wherein the voltage reference is configured to provide a reference voltage to the LDO voltage regulator and the reference current generator.

20. The semiconductor die of claim 11 wherein the power amplifier is configured to operate at a first level during transmit modes and operate at a second level during non-transmit modes.

Assignees

• Skyworks Solutions Inc

Inventors

• LIANG Bang Li
• Soliman Yasser Khairat
• Bergsma Adrian John
• Yu Haoran
• Sarbishaei Hassan

Classifications

• G05F1/575

  characterised by the feedback circuit · CPC title

• G05F1/468

  characterised by reference voltage circuitry, e.g. soft start, remote shutdown · CPC title

• G05F1/565 Primary

  sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor (G05F1/563 takes precedence) · CPC title

• G05F1/461

  using an operational amplifier as final control device · CPC title

• G05F3/225 Primary

  producing a current or voltage as a predetermined function of the temperature · CPC title