Time interleaver, time deinterleaver, time interleaving method, and time deinterleaving method

Patent metadata

Field	Value
Publication number	US-11611515-B2
Application number	US-202217887793-A
Country	US
Kind code	B2
Filing date	Aug 15, 2022
Priority date	Sep 29, 2014
Publication date	Mar 21, 2023
Grant date	Mar 21, 2023

Abstract

A convolutional interleaver included in a time interleaver, which performs convolutional interleaving includes: a first switch that switches a connection destination of an input of the convolutional interleaver to one end of one of a plurality of branches; a FIFO memories provided in some of the plurality of branches except one branch, wherein a number of FIFO memories is different among the plurality of branches; and a second switch that switches a connection destination of an output of the convolutional interleaver to another end of one of the plurality of branches. The first and second switches switch the connection destination when the plurality of cells as many as the codewords per frame have passed, by switching a corresponding branch of the connection destination sequentially and repeatedly among the plurality of branches.

First claim

The invention claimed is:

1. A transmitter comprising:
an input terminal into which cells are to be input from a block interleaver, the block interleaver including a matrix for block interleaving, the matrix having N columns, the cells being generated using low-density parity check (LDPC) coding;
an output terminal from which the cells are to be output such that each of the cells is classified in any one of M interleaving units;
a convolutional delay circuit comprising: M branches; and first in, first out (FIFO) registers to delay cells, a number of the FIFO registers provided in an M′th branch being M′-1, M′ being an integer from 1 to M;
a first switch provided between the input terminal and the convolutional delay circuit;
a second switch provided between the convolutional delay circuit and the output terminal;
a modulator that applies orthogonal frequency-division multiplexing (OFDM) modulation to the cells output from the output terminal; and
an antenna that transmits a radio wave according to the cells to which the OFDM modulation has been applied, wherein
the first switch and the second switch are each configured to connect to an identical branch of the M branches such that the input terminal and the output terminal are connected via the identical branch, and
the first switch and the second switch are each configured to connect to an L+1th branch or a first branch when N cells are input into the input terminal while the first switch and the second switch each connect to an Lth branch, L being an integer from 1 to M.

2. A transmission method comprising:
reordering cells with a matrix having N columns for block interleaving, the cells being generated using low-density parity check (LDPC) coding;
inputting the cells into a convolutional delay circuit via a first switch after the cells are reordered, the convolutional delay circuit comprising:
M branches; and
first in, first out (FIFO) registers to delay cells, a number of the FIFO registers provided in an M′th branch is M′-1, M′ being an integer from 1 to M;
outputting the cells from the convolutional delay circuit via a second switch such that each of the cells is classified in any one of M interleaving units;
applying orthogonal frequency-division multiplexing (OFDM) modulation to the cells output from the convolutional delay circuit via the second switch; and
transmitting a radio wave according to the cells to which the OFDM modulation has been applied, wherein
the first switch and the second switch each connect to an identical branch of the M branches, and
the first switch and the second switch each connect to an L+1th branch or a first branch when N cells are input into the convolutional delay circuit while the first switch and the second switch each connect to an Lth branch, L being an integer from 1 to M.

Assignees

• Panasonic Holdings Corp

Inventors

• Klenner Peter

Classifications

• H03M13/27

  using interleaving techniques · CPC title

• H04L47/6245 Primary

  Modifications to standard FIFO or LIFO · CPC title

• H03M13/271 Primary

  Row-column interleaver with permutations, e.g. block interleaving with inter-row, inter-column, intra-row or intra-column permutations · CPC title

• H03M13/6552

  DVB-T2 · CPC title

• H03M13/2785

  Interleaver using in-place interleaving, i.e. writing to and reading from the memory is performed at the same memory location · CPC title