Transistor aging reversal using hot carrier injection

Patent metadata

Field	Value
Publication number	US-11611338-B2
Application number	US-202117399760-A
Country	US
Kind code	B2
Filing date	Aug 11, 2021
Priority date	Sep 25, 2020
Publication date	Mar 21, 2023
Grant date	Mar 21, 2023

Abstract

Embodiments relate to circuit for reversing a threshold voltage shift of a transistor. The circuit includes a current mirror for sensing a transistor current and generating a mirrored current corresponding to the sensed transistor current, a gate biasing module for providing a gate bias to the transistor, and a calibration engine configured to receive the mirrored current from the current mirror and to control the gate biasing module in response to determining whether the mirrored current is outside of a predetermined range indicative of a shift in the threshold voltage of the transistor. The gate biasing module includes a gate biasing circuit configured to operate the transistor in a region where hot carrier injection (HCI) is present, and a gate switch for coupling the gate biasing circuit to a gate terminal of the transistor.

First claim

What is claimed is:

1. A transistor aging reversal circuit for reverting a shift in a threshold voltage of a transistor, comprising:
a current mirror configured to sense a transistor current and generate a mirrored current corresponding to the sensed transistor current;
a gate biasing module comprising:
a gate biasing circuit configured to generate a bias voltage, the gate biasing circuit configured to operate the transistor in a region where hot carrier injection (HCI) is present, and
a gate switch coupled to an output of the gate biasing circuit, the gate switch for coupling the gate biasing circuit to a gate terminal of the transistor;

a calibration engine coupled to the current mirror and the gate biasing module, the calibration engine configured to detect a shift in the threshold voltage of the transistor; and
a drain biasing circuit coupled to the current mirror, the drain biasing circuit comprising:
a first drain switch coupled to a first power supply, the first drain switch for coupling a drain terminal of the transistor to the first power supply during normal operation of the transistor, and
a second drain switch coupled to a second power supply, the second drain switch for coupling the drain terminal of the transistor to the second power supply, the second power supply configured to operate the transistor in the region where HCI is present.

2. The transistor aging reversal circuit of claim 1 , wherein the current mirror comprises:
a first transistor for sensing the transistor current;
a second transistor having a gate terminal coupled to a gate terminal of the first transistor, the second transistor for generating the mirrored current; and
a current mirror switch for bypassing the current mirror, the current mirror switch coupled between a source terminal of the first transistor and a drain terminal of the first transistor.

3. The transistor aging reversal circuit of claim 2 , wherein the current mirror switch is controlled to be open during a testing phase responsive to determining that the mirrored current is outside of a predetermined range indicative of the shift in the threshold voltage of the transistor, and the current mirror switch is controlled to be closed during an adjustment phase during which the transistor is operated in a mode experiencing HCI.

4. The transistor aging reversal circuit of claim 3 , wherein the current mirror switch is further controlled to be closed during normal operation of the transistor.

5. The transistor aging reversal circuit of claim 1 , wherein the gate biasing circuit comprises:
a low-dropout (LOD) regulator for generating a reference voltage;
an oscillator coupled to the LDO regulator for generating an oscillating signal; and
a charge pump for generating the bias voltage based on the oscillating signal, the bias voltage for biasing the transistor in a region of operation where hot carriers have a likelihood of being injected into a gate oxide of the transistor.

6. The transistor aging reversal circuit of claim 1 , further comprising:
a second gate switch coupled to the gate terminal of the transistor, the second gate switch for providing a nominal bias to the gate terminal of transistor.

7. The transistor aging reversal circuit of claim 1 , wherein the bias voltage configures the transistor to operate in an on-state HCI region, and the calibration engine is further configured to close the gate switch responsive to determining that the mirrored current is larger than a threshold value indicative of a decrease in the threshold voltage of the transistor.

8. The transistor aging reversal circuit of claim 1 , wherein the bias voltage configures the transistor to operate in an off-state HCI region, and the calibration engine is further configured to close the gate switch responsive to determining that the mirrored current is lower than a threshold value indicative of an increase in the threshold voltage of the transistor.

9. A method for reverting a shift in a threshold voltage of a transistor, the method comprising:
sensing a transistor current and generating a mirrored current corresponding to the sensed transistor current;
generating a bias voltage, the bias voltage for operating the transistor in a region where hot carrier injection (HCI) is present;
determining whether the mirrored current is outside of a predetermined range indicative of a shift in the threshold voltage of the transistor;
responsive to determining that the mirrored current is outside of the predetermined range, providing the bias voltage to a gate terminal of the transistor;
closing a first drain switch during normal operation, the first drain switch for coupling a drain terminal of the transistor to a first power supply; and
closing a second drain switch in response to determining that the mirrored current is outside of the predetermined range, the second drain switch for coupling the drain terminal of the transistor to a second power supply, the second power supply configured to operate the transistor in the region where HCI is present.

10. The method of claim 9 , further comprising:
opening a current mirror switch during a testing phase responsive to determining that the mirrored current is outside of the predetermined range, the current mirror switch for bypassing a current mirror configured to sense the transistor current and generate the mirrored current.

11. The method of claim 10 , further comprising:
closing the current mirror switch during normal operation, wherein the current mirror switch is further configured to couple the drain terminal of the transistor to a third power supply.

12. The method of claim 9 , wherein the bias voltage configures the transistor to operate in an on-state HCI region, and the calibration gate bias voltage is provided to the gate terminal of the transistor responsive to determining that the mirrored current is larger than a threshold value indicative of a decrease in the threshold voltage of the transistor.

13. The method of claim 9 , wherein the bias voltage configures the transistor to operate in an off-state HCI region of operation, and the bias voltage is provided to the gate terminal of the transistor responsive to determining that the mirrored current is lower than a threshold value indicative of an increase in the threshold voltage of the transistor.

14. The method of claim 9 , further comprising providing the bias voltage to the gate terminal of the transistor for a predetermined amount of time.

15. An electronic circuit, comprising:
a main transistor having a source terminal coupled to a first power supply, a drain terminal, and a gate terminal; and
an aging reversal circuit coupled to the gate terminal and the drain terminal of the main transistor, the aging reversal circuit comprising:
a current mirror coupled to the drain terminal of the main transistor, the current mirror configured to sense a transistor current of the main transistor and generate a mirrored current corresponding to the sensed transistor current,
a gate biasing module comprising:
a gate biasing circuit configured to generate a bias voltage, and
a gate switch coupled to an output of the gate biasing circuit, the gate switch for coupling the gate biasing circuit to the gate terminal of the main transistor,

a calibration engine coupled to the current mirror and the gate biasing module, the calibration engine configured to detect a shift in a threshold voltage of the main transistor, and
a drain biasing circuit coupled to the drain terminal of the main transistor, the drain biasing circuit comprising:
a first drain switch coupled to a second power

Assignees

• Apple Inc

Inventors

• Ismail Aly
• Haggag Amr

Classifications

• H03K17/14 Primary

  Modifications for compensating variations of physical values, e.g. of temperature · CPC title

• H03K17/302 Primary

  in field-effect transistor switches · CPC title

• H03K2217/0054

  Gating switches, e.g. pass gates · CPC title

• H03K2217/9401

  Calibration techniques · CPC title