Array substrate and display panel design improving aperture ratio

Patent metadata

Field	Value
Publication number	US-11610922-B2
Application number	US-201916618129-A
Country	US
Kind code	B2
Filing date	Aug 29, 2019
Priority date	Aug 8, 2019
Publication date	Mar 21, 2023
Grant date	Mar 21, 2023

Abstract

An array substrate, a display panel, and a method of fabricating an array substrate are provided. The array substrate includes a display region and a non-display region. The array substrate further includes a substrate, a first transparent layer disposed on the substrate corresponding to the display region, an interlayer insulating layer disposed on the substrate, and a second transparent layer disposed on the interlayer insulating layer.

First claim

What is claimed is:

1. An array substrate, comprising a display region and a non-display region, wherein the array substrate comprises:
a substrate;
a first transparent layer disposed on the substrate corresponding to the display region;
an interlayer insulating layer disposed on the substrate;
a second transparent layer disposed on the interlayer insulating layer;
a passivation layer disposed on the interlayer insulating layer;
a planarization layer disposed on the passivation layer;
a second contact hole penetrated through the passivation layer and the planarization layer;
a pixel electrode layer disposed on the planarization layer and connected to a metal layer through the second contact hole; and
a pixel definition layer disposed on the planarization layer and partially covered on the pixel electrode layer;
wherein the substrate positioned in the non-display region is sequentially laminated with:
an active layer disposed on the substrate, wherein the active layer is disposed in a same layer as the first transparent layer;
a gate insulating layer disposed on the active layer; and
a gate disposed on the gate insulating layer;
wherein the interlayer insulating layer comprises at least two first contact holes disposed in the interlayer insulating layer.

2. The array substrate according to claim 1 , wherein the interlayer insulating layer disposed in the non-display region is further provided with a composite metal layer disposed on the interlayer insulating layer, the composite metal layer is partially disposed in the first contact hole, the composite metal layer comprises the metal layer and a second transparent layer laminated, the second transparent layer disposed on the interlayer insulating layer, and the metal layer disposed on the second transparent layer.

3. The array substrate according to claim 2 , wherein the passivation layer is disposed on the composite metal layer.

4. The array substrate according to claim 1 , wherein the substrate comprises:
a glass substrate;
a light-shielding layer disposed on the glass substrate in the non-display region; and
a buffer layer disposed on the light-shielding layer and the glass substrate.

5. An organic light-emitting diode display panel, comprising an array substrate as claimed in claim 1 .

6. An array substrate, comprising a display region and a non-display region, wherein the array substrate comprises:
a substrate comprising:
a glass substrate;
a light-shielding layer disposed on the glass substrate in the non-display region; and
a buffer layer disposed on the light-shielding layer and the glass substrate;

a first transparent layer disposed on the substrate corresponding to the display region;
an interlayer insulating layer disposed on the substrate;
a second transparent layer disposed on the interlayer insulating layer;
a passivation layer disposed on the interlayer insulating layer;
a planarization layer disposed on the passivation layer;
a second contact hole penetrated through the passivation layer and the planarization layer;
a pixel electrode layer disposed on the planarization layer and connected to a metal layer through the second contact hole; and
a pixel definition layer disposed on the planarization layer and partially covered on the pixel electrode layer.

Assignees

• Shenzhen China Star Optoelectronics Semiconductor Display Tech Co Ltd

Inventors

• Zhou Xingyu

Classifications

• H10D86/021

  of multiple TFTs · CPC title

• H10D86/481

  integrated with passive devices, e.g. auxiliary capacitors · CPC title

• H10D30/6755

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10D30/6723

  having light shields · CPC title

• H10D86/423

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title