Release layer-assisted selective embedding of magnetic material in cored and coreless organic substrates

Patent metadata

Field	Value
Publication number	US-11610706-B2
Application number	US-201815870302-A
Country	US
Kind code	B2
Filing date	Jan 12, 2018
Priority date	Jan 12, 2018
Publication date	Mar 21, 2023
Grant date	Mar 21, 2023

Abstract

A substrate for an integrated circuit package, the substrate comprising a dielectric, at least one conductor plane within the dielectric, and a planar magnetic structure comprising an organic magnetic laminate embedded within the dielectric, wherein the planar magnetic structure is integrated within the at least one conductor plane.

First claim

What is claimed is:

1. A substrate for an integrated circuit package, the substrate comprising:
a substrate core;
a dielectric over a first side of the substrate core;
at least one conductor plane within the dielectric; and
a planar magnetic structure comprising a magnetic laminate embedded within the dielectric, wherein the magnetic laminate comprises an organic material, and wherein the planar magnetic structure overlaps one or more first metal features of the conductor plane and two opposing side edges of the magnetic laminate intersect the one or more first metal features, wherein the planar magnetic structure is a planar inductor core and wherein a second conductor plane comprises an inductor winding over the planar inductor core and on a second side of the substrate core.

2. The substrate of claim 1 , wherein the magnetic laminate includes magnetic particles embedded in a polymer matrix, and wherein the organic material includes the polymer matrix which comprises an epoxy resin.

3. The substrate of claim 2 , wherein the magnetic particles comprise one of: gamma-ferric oxide, magnetite, iron, nickel, cobalt, molybdenum, manganese, lanthanide series elements or a Heusler alloy.

4. The substrate of claim 1 , further comprising a core having a first side and a second side opposite the first side, wherein the planar magnetic structure is integrated over one of the first side of the core or the second side of the core.

5. The substrate of claim 1 , wherein the magnetic laminate has an interface with the first metal features.

6. The substrate of claim 5 , wherein a release film is between the magnetic laminate and the first metal features, and wherein an edge of the release film is also over the first metal features.

7. The substrate of claim 1 , wherein the magnetic laminate has a conformal interface with the first metal features.

8. The substrate of claim 1 , wherein the dielectric comprises an organic laminate, and wherein the magnetic laminate has an interface with the organic laminate.

9. The substrate of claim 1 , wherein the planar magnetic structure is interleaved between the first conductor plane and a second conductor plane that is over the magnetic laminate.

10. The substrate of claim 1 , wherein the planar magnetic structure has a relative magnetic permeability ranging between 5 and 20.

11. The substrate of claim 1 , wherein the planar magnetic structure has a thickness of at least 20 microns.

12. A system, comprising:
a memory;
a processor coupled to the memory; and
a wireless transceiver to allow the processor to communicate wirelessly to an external device, wherein at least one of the processor, memory or wireless transceiver are within an integrated circuit package comprising the substrate of claim 1 .

Assignees

• Intel Corp

Inventors

• Vadlamani Sai
• Chatterjee Prithwish
• Jain Rahul
• Lee Kyu Oh
• Li Sheng C
• Brown Andrew J
• Link Lauren A

Classifications

• H10W74/01

  Manufacture or treatment · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W44/501

  Inductive arrangements (H10W44/20 takes precedence) · CPC title