Low-leakage drain-programmed ROM

Patent metadata

Field	Value
Publication number	US-11610633-B2
Application number	US-202117367248-A
Country	US
Kind code	B2
Filing date	Jul 2, 2021
Priority date	Jul 2, 2021
Publication date	Mar 21, 2023
Grant date	Mar 21, 2023

Abstract

A drain programmed read-only memory includes a diffusion region that spans a width of a bitcell and forms a drain of a first transistor and a second transistor. A bit line lead in a metal layer adjacent the diffusion region extends across the width of the bitcell. A first via extends from an upper half of the bit line lead and couples to a drain of the first transistor. Similarly, a second via extends from a lower half of the bit line and couples to a drain of the second transistor.

First claim

What is claimed is:

1. A read-only memory, comprising:
a semiconductor substrate including a diffusion region configured to form a drain of a first transistor and a drain of a second transistor;
a metal layer adjacent the diffusion region, the metal layer being configured to include a bit line lead that extends across the diffusion region;
a first drain via positioned within an upper half of the bit line lead, the first drain via being configured to couple from the upper half of the bit line lead to the drain of the first transistor; and
a second drain via positioned within a lower half of the bit line lead, the second drain via configured to couple from the lower half of the bit line lead to the drain of the second transistor.

2. The read-only memory of claim 1 , wherein the diffusion region is further configured to extend across a width of a first bitcell, the first bitcell having a bitcell height extending from a lower bitcell boundary, and wherein the metal layer is further configured to include a first ground lead having a central longitudinal axis substantially aligned with the lower bitcell boundary.

3. The read-only memory of claim 2 , wherein the diffusion region is further configured to include a shared source of the first transistor and of the second transistor, the read-only memory further comprising:
a first column of local interconnect coupled to the shared source; and
a first ground via configured to couple between the first ground lead and the first column of local interconnect.

4. The read-only memory of claim 3 , wherein the metal layer is further configured to include a second ground lead having a central longitudinal axis substantially aligned with an upper boundary of the bitcell height, the read-only memory further comprising:
a second ground via configured to couple between the second ground lead and the first column of local interconnect.

5. The read-only memory of claim 3 , further comprising:
a second column of local interconnect coupled to the drain of the first transistor, wherein the first drain via is configured to extend between the upper half of the bit line lead and the second column of local interconnect.

6. The read-only memory of claim 5 , further comprising:
a third column of local interconnect coupled to the drain of the second transistor, wherein the second drain via is configured to extend between the lower half of the bit line lead and the third column of local interconnect.

7. The read-only memory of claim 4 , wherein the diffusion region is further configured to extend across a width of a second bitcell and to include within the second bitcell a drain of a third transistor and a drain of a fourth transistor, and wherein the drain of the third transistor and the drain of the fourth transistor are both electrically isolated from bit line lead.

8. The read-only memory of claim 7 , wherein the diffusion region is further configured to extend across a width of a third bitcell and to include with the third bitcell a drain of a fifth transistor and a drain of a sixth transistor, the read-only memory further comprising:
a third drain via positioned with the upper half of the bit line lead, the third drain via being configured to couple from the upper half of the bit line lead to the drain of the fifth transistor.

9. The read-only memory of claim 8 , wherein the drain of the sixth transistor is electrically isolated from the bit line lead.

10. The read-only memory of claim 8 , further comprising:
a fourth drain via positioned with the lower half of the bit line lead, the fourth drain via being configured to couple from the lower half of the bit line lead to the drain of the sixth transistor.

11. The read-only memory of claim 1 , wherein the diffusion region is doped n-type, and wherein each first transistor and each second transistor is an n-type metal-oxide-semiconductor (NMOS) transistor.

12. The read-only memory of claim 1 , wherein the diffusion region is doped p-type, and wherein each first transistor and each second transistor is a p-type metal-oxide-semiconductor (PMOS) transistor.

13. The read-only memory of claim 1 , wherein the first transistor and the second transistor are thick-gate-oxide transistors.

14. A read-only memory, comprising:
a plurality of bitcells arranged into a row within a bitcell height, each bitcell in the plurality of bitcells including a first transistor and a second transistor;
a diffusion region configured to extend across the row, the diffusion region being configured for each bitcell in the plurality of bitcells to form a drain of the bitcell's first transistor and to form a drain of the bitcell's second transistor; and
a metal layer adjacent the diffusion region, the metal layer being configured to include a bit line lead that extends across the row; wherein each bitcell in a first subset of the plurality of bitcells is configured to include a first drain via positioned on and coupled from a lower half of the bit line lead to the drain of the bitcell's first transistor and to include a second drain via positioned on and coupled from an upper half of the bit line lead to the drain of the bitcell's second transistor and, and wherein each bitcell in a second subset of the plurality of bitcells is configured to electrically isolate both the drain of the bitcell's first transistor and the drain of the bitcell's second transistor from the bit line lead.

15. The read-only memory of claim 14 , wherein each bitcell in a third subset of the plurality of bitcells is configured to include a first drain via positioned on and coupled from a lower half of the bit line lead to the drain of the bitcell's first transistor, and wherein the bitcell is configured to electrically isolate the drain of the bitcell's second transistor from the bit line lead.

16. The read-only memory of claim 15 , wherein a fourth bitcell in the plurality of bitcells is configured to include a fourth via coupled between the drain of the fourth bitcell's second transistor and the upper half of the bit line lead, wherein the drain of the fourth bitcell's first transistor is configured to be isolated from the bit line lead.

17. The read-only memory of claim 14 , wherein the metal layer is further configured to include a first ground lead having a central longitudinal axis substantially aligned with an upper boundary of the bitcell height, and wherein each bitcell in the plurality of bitcells includes a first ground via coupled between the first ground lead and a shared source of the bitcell's first transistor and second transistor.

18. The read-only memory of claim 17 , wherein the metal layer is further configured to include a second ground lead having a central longitudinal axis substantially aligned with a lower boundary of the bitcell height, and wherein each bitcell in the plurality of bitcells includes a second ground via coupled between the second ground lead and the shared source of the bitcell's first transistor and second transistor.

19. A method of operating a read-only memory, comprising;
asserting a voltage of a first word line coupled to a gate of a first transistor arranged in a row within a bitcell height with a second transistor to cause the first transistor to conduct charge from a first drain via positioned on an upper half of a bit line lead to ground through a first ground via positioned on a first ground lead having a central longitudinal axis substantially aligned with an upper boundary of the bitcell height; and
asserting a voltage of a second word line coupled to a gate of the s

Assignees

• Qualcomm Inc

Inventors

• Chen Xiao
• Hsieh Chen-Ju
• Son Sung
• Jung Chulmin

Classifications

• G11C16/102 Primary

  External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators · CPC title

• G11C17/126 Primary

  Virtual ground arrays · CPC title

• G11C16/0433

  comprising cells containing a single floating gate transistor and one or more separate select transistors · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/24

  Bit-line control circuits · CPC title