PCIe device peer-to-peer communications

Patent metadata

Field	Value
Publication number	US-11609873-B2
Application number	US-202117461149-A
Country	US
Kind code	B2
Filing date	Aug 30, 2021
Priority date	Feb 5, 2019
Publication date	Mar 21, 2023
Grant date	Mar 21, 2023

Abstract

Computing architectures, platforms, and systems are provided herein. In one example, system is provided. The system includes a first processor configured to initiate a communication arrangement between a first peripheral component interconnect express (PCIe) device and a second PCIe device. The communication arrangement is configured to detect transfers from the first PCIe device to one or more addresses corresponding to an address range of the second PCIe device, and redirect the transfers to the second PCIe device without passing the transfers through a second processor that initiates the transfers.

First claim

What is claimed is:

1. A system comprising:
a user interface configured to receive instructions to initiate a communication arrangement between a first peripheral component interconnect express (PCIe) device and a second PCIe device;
wherein the communication arrangement is configured to redirect a transfer from the first PCIe device based on an address corresponding to an address range of the second PCIe device without passing the transfer through a host processor that executes an application initiating the transfer.

2. The system of claim 1 , wherein the communication arrangement is established in a PCIe fabric comprising one or more PCIe switch circuits.

3. The system of claim 1 , wherein the first PCIe device comprises a Graphics Processing Unit (GPU) and the second PCIe device comprises a storage device.

4. The system of claim 1 , wherein the communication arrangement is further established to detect an additional transfer from the second PCIe device to one or more addresses corresponding to an address range for the first PCIe device, and redirect the additional transfer to the first PCIe device without passing the additional transfer through the host processor that initiates the additional transfer.

5. The system of claim 1 , wherein the address range of the second PCIe device is in addition to a memory mapped address range assigned to the second PCIe device within a memory space of the host processor during enumeration of the second PCIe device by the host processor.

6. The system of claim 1 , wherein the transfer is initiated by a request originated by the application executed by the host processor to transfer data from the first PCIe device to the second PCIe device via a command that employs the communication arrangement.

7. The system of claim 1 , wherein a management driver executed by the host processor interfaces with a first device driver associated with the first PCIe device at least to initiate a direct memory access (DMA) transfer via the first device driver with a destination address corresponding to the address range for the second PCIe device.

8. The system of claim 1 , wherein the communication arrangement redirects the transfer from the first PCIe device directed to the one or more addresses corresponding to the address range for the second PCIe device at least in part by translating the one or more addresses into PCIe device physical addresses of the second PCIe device.

9. A method comprising:
receiving, via a user interface, instructions initiating a communication arrangement between a first peripheral component interconnect express (PCIe) device and a second PCIe device;
wherein the communication arrangement is configured to redirect a transfer from the first PCIe device based on an address corresponding to an address range of the second PCIe device without passing the transfer through a host processor that executes an application initiating the transfer.

10. The method of claim 9 , wherein the communication arrangement is established in a PCIe fabric comprising one or more PCIe switch circuits.

11. The method of claim 9 , wherein the first PCIe device comprises a Graphics Processing Unit (GPU) and the second PCIe device comprises a storage device.

12. The method of claim 9 , wherein at least one transfer is initiated by a request originated by the application executed by the host processor to transfer data from the first PCIe device to the second PCIe device via a command that employs the communication arrangement.

13. The method of claim 9 , wherein a management driver of the host processor interfaces with a first device driver associated with the first PCIe device at least to initiate a direct memory access (DMA) transfer via the first device driver with a destination address corresponding to the address range for the second PCIe device.

14. The method of claim 9 , wherein the communication arrangement redirects the transfer from the first PCIe device directed to the one or more addresses corresponding to the address range for the second PCIe device at least in part by translating the one or more addresses into PCIe device physical addresses of the second PCIe device.

15. An apparatus comprising:
one or more computer readable storage media;
program instructions stored on the one or more computer readable storage media, that when executed by a processor, direct the processor to at least:
receive, via a user interface, instructions to initiate a communication arrangement between a first peripheral component interconnect express (PCIe) device and a second PCIe device;
wherein the communication arrangement is configured to redirect a transfer from the first PCIe device based on an address corresponding to an address range of the second PCIe device without passing the transfer through a host processor that executes an application initiating the transfer.

16. The apparatus of claim 15 , wherein the communication arrangement is established over a PCIe fabric comprising one or more PCIe switch circuits.

17. The apparatus of claim 15 , wherein the address range of the second PCIe device is in addition to a memory mapped address range assigned to the second PCIe device within a memory space of the host processor during enumeration of the second PCIe device by the host processor.

18. The apparatus of claim 15 , wherein the transfer is initiated by a request originated by the application executed by the host processor to transfer data from the first PCIe device to the second PCIe device via a command that employs the communication arrangement.

19. The apparatus of claim 15 , wherein a management driver executed by the host processor interfaces with a first device driver associated with the first PCIe device at least to initiate a direct memory access (DMA) transfer via the first device driver with a destination address corresponding to the address range for the second PCIe device.

20. The apparatus of claim 15 , wherein the communication arrangement redirects the transfer from the first PCIe device directed to the one or more addresses corresponding to the address range for the second PCIe device at least in part by translating the one or more addresses into PCIe device physical addresses of the second PCIe device.

Assignees

• Liqid Inc

Inventors

• Cannata James Scott
• Long Christopher R
• Puri Sumit
• Schramm Bryan

Classifications

• G06F13/28 Primary

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F2213/0026

  PCI express · CPC title

• G06F13/4234

  being a memory bus · CPC title

• G06F13/4221

  being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus · CPC title

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title