Semiconductor device and potential measurement apparatus

Patent metadata

Field	Value
Publication number	US-11606071-B2
Application number	US-201816756544-A
Country	US
Kind code	B2
Filing date	Oct 23, 2018
Priority date	Oct 23, 2017
Publication date	Mar 14, 2023
Grant date	Mar 14, 2023

Abstract

To provide a semiconductor device that makes it possible to reduce a cell circuit area and an increase in resolution. There is provided a semiconductor device including: a first region in which readout cells are arranged in an array form, the readout cells having one of input transistors included in a differential amplifier: and a second region in which reference cells are arranged in an array form, the reference cells having another input transistor included in the differential amplifier, the first region and the second region being separated from each other.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first region in which readout cells are arranged in an array form, the readout cells having one input transistor included in a differential amplifier; and
a second region in which reference cells are arranged in an array form, the reference cells having another input transistor included in the differential amplifier,
wherein the second region includes two portions, a first portion provided on a first side of the first region and a second portion provided on a second side of the first region,
wherein the first portion of the second region and the second portion of the second region are provided on opposite sides of the first region,
wherein a plurality of output signal lines from the differential amplifier are provided in parallel, and a plurality of the differential amplifiers are simultaneously turned to an operation state to simultaneously read outputs from the plurality of the differential amplifiers.

2. The semiconductor device according to claim 1 , wherein the first region is a region in which a potential of a signal is measured, and
wherein the second region is a region in which a reference potential is set.

3. The semiconductor device according to claim 1 , wherein the differential amplifier includes a current mirror circuit and a current source provided either above or below the first and second regions in a vertical direction.

4. The semiconductor device according to claim 3 , wherein distances in the vertical direction between the current mirror circuit and the current source for each of the first region, the first portion of the second region and the second portion of the second region are substantially equal.

5. The semiconductor device according to claim 3 , wherein a plurality of the readout cells correspond to one of the reference cells disposed in the second region to configure the differential amplifier.

6. The semiconductor device according to claim 3 , wherein, in the differential amplifier, an electrode is coupled to the one input transistor coupled to the current mirror that is diode-coupled, and an output is coupled to the another input transistor through a capacitor.

7. The semiconductor device according to claim 1 , wherein a plurality of the readout cells correspond to one of the reference cells disposed in the second region to configure the differential amplifier.

8. A potential measurement apparatus, comprising:
a semiconductor device, comprising:
a first region in which readout cells are arranged in an array form, the readout cells having one input transistor included in a differential amplifier; and
a second region in which reference cells are arranged in an array form, the reference cells having another input transistor included in the differential amplifier;

a horizontal selection circuit that selects a readout cell and a reference cell of semiconductor device; and
an A/D conversion circuit that converts an analog signal outputted from the semiconductor device into a digital signal,
wherein the A/D conversion circuit includes a comparator circuit that compares a predetermined reference potential with an output from the semiconductor device, and
wherein the comparator circuit includes an amplifier in a first stage, an amplifier in a second stage, and a Miller capacitance coupled between the amplifier in the first stage and the amplifier in the second stage.

9. The potential measurement apparatus according to claim 8 , wherein the second region is provided on a side opposed to a side in which the A/D conversion circuit is provided with the first region interposed therebetween.

10. The potential measurement apparatus according to claim 8 , wherein a plurality of the A/D conversion circuits are provided, and wherein one A/D conversion circuit is provided at each position between which the semiconductor device is interposed.

11. The potential measurement apparatus according to claim 10 , wherein multiple A/D conversion circuits of the plurality of the A/D conversion circuits are provided at each of the positions between which the semiconductor device is interposed.

12. The potential measurement apparatus according to claim 10 , wherein a plurality second regions are provided, wherein the first region of the semiconductor device is provided at a position interposed between the plurality of second regions, and wherein one A/D conversion circuit is provided at each position between which the plurality of second regions are interposed.

13. The potential measurement apparatus according to claim 10 , wherein a plurality second regions are provided, wherein the first region of the semiconductor device is provided at a position interposed between the plurality of second regions, and wherein the A/D conversion circuit is provided at positions perpendicular to the plurality of second regions.

14. The potential measurement apparatus according to claim 8 , wherein a plurality of the A/D conversion circuits are provided on one side of the semiconductor device.

15. The potential measurement apparatus according to claim 8 , wherein the A/D conversion circuit converts an analog signal outputted from the semiconductor device into a digital signal by oversampling.

16. The potential measurement apparatus according to claim 8 , wherein the A/D conversion circuit is driven to execute digital integration processing in which n-bit AD conversion (where n is an integer of 1 or greater) is repeated W times (where W is an integer of 2 or greater).

17. The potential measurement apparatus according to claim 8 , further comprising:
a first chip in which a portion or an entirety of the A/D conversion circuit is formed; and
a second chip on which the first chip is stacked and in which a configuration other than a configuration formed in the first chip is formed.

18. The potential measurement apparatus according to claim 17 , wherein a plurality of the first chips are stacked on the second chip.

Assignees

• Sony Semiconductor Solutions Corp

Inventors

• Kato Yuri

Classifications

• H04N25/77

  Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components · CPC title

• H03F3/45753

  using switching means, e.g. sample and hold · CPC title

• H03F2203/45101

  Control of the DC level being present · CPC title

• H03F3/68 Primary

  Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics {(power amplifiers using a combination of several semiconductor amplifiers H03F3/211; combinations of amplifiers using coupling networks with distributed constants H03F3/602)} · CPC title

• H03F2203/45674

  the LC comprising one current mirror · CPC title