Time-based frequency tuning of analog-to-information feature extraction

Patent metadata

Field	Value
Publication number	US-11605372-B2
Application number	US-202217702253-A
Country	US
Kind code	B2
Filing date	Mar 23, 2022
Priority date	Oct 22, 2015
Publication date	Mar 14, 2023
Grant date	Mar 14, 2023

Abstract

A sound recognition system including time-dependent analog filtered feature extraction and sequencing. An analog front end (AFE) in the system receives input analog signals, such as signals representing an audio input to a microphone. Features in the input signal are extracted, by measuring such attributes as zero crossing events and total energy in filtered versions of the signal with different frequency characteristics at different times during the audio event. In one embodiment, a tunable analog filter is controlled to change its frequency characteristics at different times during the event. In another embodiment, multiple analog filters with different filter characteristics filter the input signal in parallel, and signal features are extracted from each filtered signal; a multiplexer selects the desired features at different times during the event.

First claim

What is claimed is:

1. A method comprising:
receiving, by a first filter, an analog signal having a plurality of frames, wherein the first filter includes a first frequency response;
receiving, by a second filter, the analog signal, wherein the second filter includes a second frequency response different than the first frequency response;
filtering, by the first filter, the analog signal to produce a first filtered signal;
filtering, by the second filter, the analog signal to produce a second filtered signal;
receiving, by each of a plurality of feature extraction circuits, one of the first filtered signal and the second filtered signal;
outputting, by each of the plurality of feature extraction circuits, respective outputs; and
selecting, by a multiplexer in response to a selection signal, one of the respective outputs for each frame of a subset of the plurality of frames to output a feature sequence.

2. The method of claim 1 , wherein:
the plurality of feature extraction circuits includes a first feature extraction circuit, a second feature extraction circuit, and a third feature extraction circuit;
the respective outputs include a first feature extraction output associated with the first feature extraction circuit, a second feature extraction output associated with the second feature extraction circuit, and a third feature extraction output associated with the third feature extraction circuit;
selecting, by the multiplexer in response to the selection signal, one of the respective outputs includes selecting the first feature extraction output at a first frame to output a first feature in the feature sequence;
selecting, by the multiplexer in response to the selection signal, one of the respective outputs includes selecting the second feature extraction output at a second frame to output a second feature in the feature sequence subsequent to the first feature; and
selecting, by the multiplexer in response to the selection signal, one of the respective outputs includes selecting one of the first feature extraction output and the second feature extraction output at a third frame to output a third feature in the feature sequence subsequent to the second feature.

3. The method of claim 1 , wherein:
a time base controller issues the selection signal.

4. The method of claim 1 , wherein:
the filtering, by the first filter, and the filtering, by the second filter, occur in parallel.

5. The method of claim 1 , further comprising:
performing, by an analog-to-digital converter, analog-to-digital conversion of the feature sequence to form a digitized feature sequence.

6. The method of claim 1 , further comprising:
receiving, by an event trigger, the feature sequence.

7. The method of claim 6 , further comprising:
comparing, by a processor, the feature sequence with a pre-defined feature sequence; and
in response to the comparing indicating a match, wake up the processor.

8. The method of claim 7 , further comprising:
in response to the processor waking up, performing, by the processor, a sound recognition process on the analog signal.

9. A circuit comprising:
a first filter configured to:
receive an analog signal having a plurality of frames, wherein the first filter includes a first frequency response; and
filter the analog signal to produce a first filtered signal;
a second filter configured to:
receive the analog signal, wherein the second filter includes a second frequency response different than the first frequency response; and
filter the analog signal to produce a second filtered signal;
a plurality of feature extraction circuits configured to:
receive one of the first filtered signal and the second filtered signal; and
output respective outputs; and
a multiplexer configured to select, in response to a selection signal, one of the respective outputs for each frame of a subset of the plurality of frames to output a feature sequence.

10. The circuit of claim 9 , wherein:
the plurality of feature extraction circuits includes a first feature extraction circuit, a second feature extraction circuit, and a third feature extraction circuit;
the respective outputs include a first feature extraction output associated with the first feature extraction circuit, a second feature extraction output associated with the second feature extraction circuit, and a third feature extraction output associated with the third feature extraction circuit;
the multiplexer is configured to select, in response to the selection signal, the first feature extraction output at a first frame to output a first feature in the feature sequence;
the multiplexer is configured to select, in response to the selection signal, the second feature extraction output at a second frame to output a second feature in the feature sequence subsequent to the first feature; and
the multiplexer is configured to select, in response to the selection signal, one of the first feature extraction output and the second feature extraction output at a third frame to output a third feature in the feature sequence subsequent to the second feature.

11. The circuit of claim 9 , wherein:
a time base controller issues the selection signal.

12. The circuit of claim 9 , wherein:
the first filter and the second filter are configured to perform filtering in parallel.

13. The circuit of claim 9 , further comprising:
an analog-to-digital converter configured to perform analog-to-digital conversion of the feature sequence to form a digitized feature sequence.

14. The circuit of claim 9 , further comprising:
an event trigger configured to receive the feature sequence.

15. The circuit of claim 14 , further comprising:
a processor configured to:
compare the feature sequence with a pre-defined feature sequence; and
in response to the comparing indicating a match, enter into a full operational mode from a restricted operational mode.

16. The circuit of claim 15 , wherein:
in response to the processor entering the full operational mode, the processor is configured to perform a sound recognition process on the analog signal.

Assignees

• Texas Instruments Inc

Inventors

• Zhang Zhenyong
• Ma Wei

Classifications

• G10L15/30

  Distributed recognition, e.g. in client-server systems, for mobile phones or network applications · CPC title

• G10L15/02 Primary

  Feature extraction for speech recognition; Selection of recognition unit · CPC title

• G10L25/09

  the extracted parameters being zero crossing rates · CPC title

• G10L15/32

  Multiple recognisers used in sequence or in parallel; Score combination systems therefor, e.g. voting systems · CPC title

• G10L21/0224

  Processing in the time domain · CPC title