Processor socket bridge for input/output extension

Patent metadata

Field	Value
Publication number	US-11604755-B2
Application number	US-202117196124-A
Country	US
Kind code	B2
Filing date	Mar 9, 2021
Priority date	Mar 9, 2021
Publication date	Mar 14, 2023
Grant date	Mar 14, 2023

Abstract

Presented herein are improvement to computer system architecture. In one embodiment, a method includes reconfiguring system interconnect links disposed between a first central processing unit socket and a second central processing unit socket, disposed together on a single motherboard, as peripheral bus links; and transmitting electrical signals, via the peripheral bus links, and via a printed circuit board that bridges the second central processing unit socket, to at least one input/output functional block that is disposed on the single motherboard and that is selectively connectable to the second central processing unit socket.

First claim

What is claimed is:

1. An apparatus comprising:
a motherboard;
a first central processing unit socket mounted on the motherboard;
a second central processing unit socket mounted on the motherboard;
a first connector, separate from the first central processing unit socket and the second central processing unit socket, in communication with the first central processing unit socket;
a second connector, separate from the first central processing unit socket and the second central processing unit socket, in communication with at least one input/output functional block that is disposed on the motherboard and that is configured to support a second central processing unit deployable in the second central processing unit socket; and
a mezzanine printed circuit board that electrically connects the first central processing unit socket with the at least one input/output functional block via the first connector and the second connector.

2. The apparatus of claim 1 , wherein the mezzanine printed circuit board extends over the second central processing unit socket.

3. The apparatus of claim 1 , further comprising a first central processing unit disposed in the first central processing unit socket.

4. The apparatus of claim 1 , wherein the mezzanine printed circuit board comprises a first mezzanine connector and a second mezzanine connector that correspond to and fit into, respectively, the first connector and the second connector.

5. The apparatus of claim 1 , wherein the mezzanine printed circuit board comprises a processor.

6. The apparatus of claim 5 , wherein the mezzanine printed circuit board comprises a first set of electrical connections that pass directly between the first connector and the second connector, and a second set of electrical connections that pass through the processor.

7. The apparatus of claim 5 , wherein the processor is configured to re-time or re-drive electrical signals exchanged between a first central processing unit disposed in the first central processing unit socket and the at least one input/output functional block.

8. The apparatus of claim 5 , wherein the mezzanine printed circuit board further comprises a switch.

9. The apparatus of claim 8 , wherein the mezzanine printed circuit board comprises a cable connector in communication with the switch.

10. The apparatus of claim 1 , wherein the mezzanine printed circuit board electrically connects the first central processing unit socket with the at least one input/output functional block via a peripheral computer interface express (PCIe) bus.

11. The apparatus of claim 1 , wherein the at least one input/output functional block comprises a network interface card, an add-in card, a dual in-line memory module, a non-volatile memory express (NVMe) storage device, a host bus adaptor, and/or a hard disk drive.

12. A method comprising:
reconfiguring system interconnect links disposed between a first central processing unit socket and a second central processing unit socket, disposed together on a single motherboard, as peripheral bus links; and
transmitting electrical signals, via the peripheral bus links, and via a printed circuit board that physically bridges over the second central processing unit socket and that is connected to the single motherboard via connectors that are separate from the first central processing unit socket and the second central processing unit socket, to at least one input/output functional block that is disposed on the single motherboard and that is selectively connectable to the second central processing unit socket.

13. The method of claim 12 , further comprising connecting the printed circuit board to the system interconnect links via a first connector on the single motherboard and a corresponding second connector on the printed circuit board.

14. The method of claim 12 , wherein the printed circuit board comprises a processor.

15. The method of claim 14 , further comprises transmitting a first portion of the electrical signals directly between the system interconnect links and the at least one input/output functional block, and transmitting a second portion of the electrical signals to the processor.

16. The method of claim 14 , further comprising at east one of re-timing or re-driving the electrical signals.

17. The method of claim 14 , further comprising switching at least a portion of the electrical signals to a different path separate from the peripheral bus links.

18. The method of claim 17 , further comprising transmitting the at least a portion of the electrical signals via a cable connector.

19. A non-transitory computer readable storage media encoded with instructions that, when executed by a processor, cause the processor to:
reconfigure system interconnect links disposed between a first central processing unit socket and a second central processing unit socket, disposed together on a single motherboard, as peripheral bus links; and
transmit electrical signals, via the peripheral bus links, and via a printed circuit board that physically bridges over the second central processing unit socket and that is connected to the single motherboard via connectors that are separate from the first central processing unit socket and the second central processing unit socket, to at least one input/output functional block that is disposed on the single motherboard and that is selectively connectable to the second central processing unit socket.

20. The non-transitory computer readable storage media of claim 19 , encoded with instructions that, when executed by the processor, cause the processor to at least one of re-time or re-drive the electrical signals.

Assignees

• Cisco Tech Inc

Inventors

• Balachandran Jayaprakash
• Sen Bidyut Kanti
• Lieu Kenny
• Mattur Dattatri N

Classifications

• H05K7/10

  Plug-in assemblages of components {, e.g. IC sockets} · CPC title

• G06F13/409

  Mechanical coupling (back panels H05K7/1438) · CPC title

• G06F13/4068 Primary

  Electrical coupling · CPC title