Single use execution environment for on-demand code execution

Patent metadata

Field	Value
Publication number	US-11604669-B2
Application number	US-202016782873-A
Country	US
Kind code	B2
Filing date	Feb 5, 2020
Priority date	Feb 5, 2020
Publication date	Mar 14, 2023
Grant date	Mar 14, 2023

Abstract

Systems and methods are provided for efficiently configuring an execution environment for an on-demand code execution system to handle a single request (or session) for a single user. Once the session or request is complete, the execution environment is reset, such as by having the hardware processor state, memory, and storage reset. In particular, prior to the execution of code, state of the execution environment of the host computing device is retrieved, such as hardware processor(s), memory, and/or storage state. Moreover, during execution of the code instructions, intermediate state can be gathered. Following the execution of the code, the execution environment is reset based on the saved state related to the hardware processor(s), memory, and/or storage. A subsequent code execution securely occurs in the execution environment and the execution environment is reset again, and so forth.

First claim

What is claimed is:

1. A computer implemented method comprising:
under control of a computer hardware processor configured with specific computer executable instructions,
receiving, from a host computing device in an on-demand code execution system, first hardware processor state from a hardware processor of the host computing device;
receiving, from the host computing device, first storage device state from a storage device of the host computing device;
causing code instructions to execute in an execution environment on a virtual machine instance of the host computing device;
while causing the code instructions to execute in the execution environment on the virtual machine instance of the host computing device,
receiving, from the host computing device, memory device state from a memory device of the host computing device, wherein causing the code instructions to execute causes:
the hardware processor of the host computing device to change to a second hardware processor state,
the storage device of the host computing device to change to a second storage device state, and
the memory device of the host computing device to change in state; and

resetting the execution environment on the virtual machine instance of the host computing device, wherein resetting the execution environment further comprises:
transmitting reset instructions to the hardware processor of the host computing device, wherein the reset instructions are configured to:
cause the hardware processor of the host computing device to revert to the first hardware processor state, and
flush a cache of the hardware processor;

causing the storage device of the host computing device to revert back to the first storage device state; and
causing the memory device of the host computing device to revert to an initial state based at least in part on the memory device state.

2. The computer implemented method of claim 1 , wherein causing the code instructions to execute causes:
recording, in the host computing device, the memory device state that indicates a memory page that was accessed or modified.

3. The computer implemented method of claim 2 , wherein recording the memory device state that indicates the memory page that was accessed further comprises:
generating a duplicate memory page of the memory page that was accessed.

4. The computer implemented method of claim 3 , wherein causing the memory device of the host computing device to revert to the initial state based at least in part on the memory device state further comprises discarding the duplicate memory page.

5. The computer implemented method of claim 2 , wherein recording the memory device state that indicates the memory page that was accessed further comprises:
generating a duplicate memory page of the memory page that was modified.

6. A system comprising:
a data storage medium; and
one or more computer hardware processors in communication with the data storage medium, the one or more computer hardware processors configured to execute computer-executable instructions to at least:
receive, from a host computing device in an on-demand code execution system, first hardware processor state from a hardware processor of the host computing device;
cause first code instructions to execute in an execution environment on a virtual machine instance of the host computing device;
while causing the first code instructions to execute in the execution environment on the virtual machine instance of the host computing device, the one or more computer hardware processors is further configured to:
receive, from the host computing device, memory device state from a memory device of the host computing device, wherein to cause the first code instructions to execute causes:
the hardware processor of the host computing device to change to a second hardware processor state, and
the memory device of the host computing device to change in state; and

reset the execution environment on the virtual machine instance of the host computing device, wherein to reset the execution environment, the one or more computer hardware processors is further configured to:
transmit reset instructions to the hardware processor of the host computing device, wherein the reset instructions are configured to:
cause the hardware processor of the host computing device to revert to the first hardware processor state, and
flush a cache of the hardware processor; and

cause the memory device of the host computing device to revert to an initial state based at least in part on the memory device state.

7. The system of claim 6 , wherein to cause the first code instructions to execute, the host computing device is further configured to:
create a bit map that indicates at least a first clean memory page and a second memory page that has been accessed or modified, wherein the memory device state indicates that the second memory page has been accessed or modified.

8. The system of claim 7 , wherein to cause the memory device of the host computing device to revert to the initial state based at least in part on the memory device state, the one or more computer hardware processors is further configured to:
identify, using the bit map, the first clean memory page and the second memory page that has been accessed or modified;
maintain the first clean memory page; and
replace the second memory page that has been accessed or modified with a clean second memory page.

9. The system of claim 6 , wherein the host computing device further comprises a reset device, wherein the reset device comprises a processor of the one or more computer hardware processors configured to transmit the reset instructions to the hardware processor of the host computing device.

10. The system of claim 6 , wherein to cause the memory device of the host computing device to revert to the initial state, at least a portion of the memory device is instructed to power off and power on.

11. The system of claim 6 , wherein the first code instructions are received from a first user computing device, and wherein the one or more computer hardware processors is further configured to:
receive, from a second user computing device different from the first user computing device, second code instructions; and
cause the second code instructions to execute in the execution environment on the virtual machine instance of the host computing device.

12. A system comprising:
a data storage medium; and
one or more computer hardware processors in communication with the data storage medium, the one or more computer hardware processors configured to execute computer-executable instructions to at least:
receive, from a first host computing device in an on-demand code execution system, first hardware processor state from a hardware processor of the first host computing device;
while first code instructions execute in a first execution environment on a first virtual machine instance of the first host computing device,
receive, from the first host computing device, memory device state from a memory device of the first host computing device, wherein to cause the first code instructions to execute causes:
the hardware processor of the first host computing device to change to a second hardware processor state, and
the memory device of the first host computing device to change in state; and

reset the first execution environment on the first virtual machine instance of the first host computing device, wherein to reset the first execution environment, the one or more computer hardware processors is further configured to:
transmit reset instructions to the hardware processor of the first host computing device, wherein the re

Assignees

• Amazon Tech Inc

Inventors

• Brooker Marc
• Danilov Mikhail
• Surkatty Osman
• Chen Tao

Classifications

• G06F2009/4557

  Distribution of virtual machine instances; Migration and load balancing · CPC title

• G06F2009/45583

  Memory management, e.g. access or allocation · CPC title

• G06F9/45558 Primary

  Hypervisor-specific management and integration aspects · CPC title

• G06F12/0804

  with main memory updating (G06F12/0806 takes precedence) · CPC title

• G06F12/0882

  Page mode · CPC title