System for executing new instructions and method for executing new instructions

Patent metadata

Field	Value
Publication number	US-11604643-B2
Application number	US-202117471400-A
Country	US
Kind code	B2
Filing date	Sep 10, 2021
Priority date	Dec 29, 2020
Publication date	Mar 14, 2023
Grant date	Mar 14, 2023

Abstract

A method for executing new instructions includes the following steps. An instruction is received. A determination is made as to whether the received instruction is a new instruction. When the received instruction is the new instruction, a emulation flag is generated. The emulation flag is a first value. A system management interrupt is generated according to the emulation flag. In response to the system management interrupt, entering the system management mode and simulating the execution of the received instruction in the system management mode to generate a simulation execution result. The simulation execution result is stored in a system management memory.

First claim

What is claimed is:

1. A method for executing new instructions, comprising:
receiving an instruction; and
determining whether the received instruction is a new instruction;
wherein when the received instruction is the new instruction:
generating a emulation flag; wherein the emulation flag is a first value;
according to the emulation flag, generating a system management interrupt;

in response to the system management interrupt, entering a system management mode, and simulating the execution of the received instruction in the system management mode to generate a simulation execution result; and
storing the simulation execution result into a system management memory.

2. The method for executing new instructions of claim 1 , wherein when the received instruction is the new instruction, the method for executing new instructions further comprises:
decoding the received instruction into a microinstruction, wherein the microinstruction includes the emulation flag; and
generating the system management interrupt according to the emulation flag in the microinstruction.

3. The method for executing new instructions of claim 2 , wherein when the received instruction is the new instruction, the method for executing new instructions further comprises:
generating the system management interrupt according to the emulation flag of the microinstruction when submitting the microinstruction.

4. The method for executing new instructions of claim 2 , wherein when the received instruction is the new instruction, the microinstruction is a no-operation microinstruction.

5. The method for executing new instructions of claim 2 , wherein when the received instruction is the new instruction, if the received instruction needs to access memory, the microinstruction is a special microinstruction, and the method for executing new instruction further comprises:
when the emulation flag of the special microinstruction is the first value, using the special microinstruction to check permissions of the received instruction, and generating a check result.

6. The method for executing new instructions of claim 5 , wherein when the received instruction is the new instruction, the method for executing new instructions further comprises:
storing the check result in a private register; and
reading the check result from the private register, and storing the read check result into the system management memory.

7. The method for executing new instructions of claim 5 , wherein the check result comprises a virtual address, a physical address, and an error code.

8. The method for executing new instructions of claim 1 , wherein when the received instruction is the new instruction, the method for executing new instructions further comprises:
storing the emulation flag in an emulation flag field of a private register; and
entering the system management mode according to the emulation flag in the private register.

9. The method for executing new instructions of claim 1 , wherein when the received instruction is the new instruction, the method for executing new instructions further comprises:
storing basic instruction information and operating environment information of the received instruction in the system management memory; and
in the system management mode, simulating the execution of the received instruction according to the basic instruction information and the operating environment information stored in the system management memory.

10. The method for executing new instructions of claim 9 , wherein when the received instruction is the new instruction, the method for executing new instructions further comprises:
decoding the received instruction to obtain the basic instruction information of the received instruction;
storing the basic instruction information of the received instruction in a private register; and;
reading the basic instruction information from the private register, and storing the read basic instruction information in the system management memory.

11. The method for executing new instructions of claim 9 , wherein the basic instruction information comprises an instruction pointer, escape code, operation code, length, and operand mode of the received instruction, and the operating environment information includes an operation mode.

12. The method for executing new instructions of claim 1 , wherein when the received instruction is the new instruction, the method for executing new instructions further comprises:
exiting the system management mode according to the simulation execution result in the system management memory.

13. The method for executing new instructions of claim 12 , wherein the simulation execution result comprises an exception flag, and when the exception flag is a first exception value, the step of exiting the system management mode according to the simulation execution result in the system management memory comprises:
reading an exception code from the simulation execution result of the system management memory;
determining exception type based on the exception code; and
when the exception is a trap, using the simulation execution result stored in the system management memory to restore the value of an architecture register, and executing a microcode handler of the exception corresponding to the exception code.

14. The method for executing new instructions of claim 12 , wherein the simulation execution result comprises an exception flag, and when the exception flag is a first exception value, the step of exiting the system management mode according to the simulation execution result in the system management memory comprises:
reading an exception code from the simulation execution result of the system management memory;
determining the exception type based on the exception code; and
when the exception is not a trap, executing a microcode handler of the exception corresponding to the exception code.

15. The method for executing new instructions of claim 12 , wherein the simulation execution result comprises an exception flag, and when the exception flag is a second exception value, the step of exiting the system management mode according to the simulation execution result in the system management memory comprises:
using the simulation execution result stored in the system management memory to restore the value of an architecture register; and
exiting the system management mode.

16. An system for executing new instructions, comprising:
a system management memory; and
an instruction monitoring unit, configured to determine whether the received instruction is a new instruction;
when the received instruction is the new instruction, the system for executing the new instructions generates an emulation flag, and generates a system management interrupt based on the emulation flag; in response to the system management interrupt, a system management mode is entered, and in the management mode, the execution of the received instruction is simulated to generate a simulation execution result; the simulation execution result is stored in the system management memory, wherein the emulation flag is a first value.

17. The system for executing new instructions of claim 16 , further comprising:
an instruction decoding unit, coupled to the instruction monitoring unit, the instruction decoding unit decodes the received instruction into a microinstruction, wherein the microinstruction includes the emulation flag; and
an instruction retiring unit, configured to generate the system management interrupt according to the emulation flag in the microinstruction.

Assignees

• Shanghai Zhaoxin Semiconductor Co Ltd

Inventors

• Wang Weilin
• Guan Yingbing
• Yang Mengchen

Classifications

• G06F9/30145

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• G06F9/223 Primary

  Execution means for microinstructions irrespective of the microinstruction function, e.g. decoding of microinstructions and nanoinstructions; timing of microinstructions; programmable logic arrays; delays and fan-out problems · CPC title

• G06F9/455 Primary

  Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines · CPC title

• G06F9/3861

  Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00) · CPC title

• G06F9/30174

  for non-native instruction set, e.g. Javabyte, legacy code · CPC title