System and method of performing discrete frequency transform for receivers using single-bit analog to digital converters

Patent metadata

Field	Value
Publication number	US-11601133-B2
Application number	US-202017081707-A
Country	US
Kind code	B2
Filing date	Oct 27, 2020
Priority date	Oct 27, 2020
Publication date	Mar 7, 2023
Grant date	Mar 7, 2023

Abstract

A system and method for performing discrete frequency transform including a pair of single-bit analog to digital converters (ADCs), a phase converter, a memory, a discrete frequency transform converter and summation circuitry. The ADCs convert an analog input signal into N pairs of binary in-phase and quadrature component samples each being one of four values at a corresponding one of four phases. The phase converter determines a phase value for each pair of component samples. The memory stores a set of discrete frequency transform coefficient values based on N. The discrete frequency transform converter uses a phase value and a pair of discrete frequency transform coefficient values retrieved from the memory for a selected frequency bin to determine a discrete frequency component for each pair of phase component samples. The summation circuitry sums the corresponding N frequency domain components for determining a frequency domain value for the selected frequency bin.

First claim

The invention claimed is:

1. A system for performing discrete frequency transform, comprising:
first and second single-bit analog to digital converters for converting an analog input signal into N pairs of binary in-phase and quadrature component samples, wherein N is a predetermined number of samples and wherein each of the N pairs of binary in-phase and quadrature phase component samples comprises one of four values with a corresponding one of four phases;
a phase converter that determines a phase value for each of the N pairs of binary in-phase and quadrature phase component samples;
a memory that stores a plurality of discrete frequency transform coefficient values based on N;
a discrete frequency transform converter that uses a corresponding phase value and a corresponding pair of discrete frequency transform coefficient values retrieved from the memory for a selected frequency bin to determine a corresponding discrete frequency component for each of the N pairs of binary in-phase and quadrature phase component samples; and
summation circuitry that sums the corresponding N frequency domain components to provide a complex summation value used for determining a frequency domain value for the selected frequency bin.

2. The system of claim 1 , wherein the discrete frequency transform converter determines an initial index into the memory for a corresponding discrete frequency transform coefficient, adjusts the index by adding a phase offset to the initial index based on the phase value to determine an adjusted index, and retrieves a real transform coefficient value and a corresponding imaginary transform coefficient value from the memory using the adjusted index.

3. The system of claim 2 , wherein the memory stores N/4 real transform coefficient values each corresponding one of N/4 component samples, wherein the discrete frequency transform converter applies a first modulo function to the adjusted index to determine a quadrant value, applies a second modulo function to the adjusted index to determine a quarter-wave index, uses the quarter-wave index and negated version of the quarter-wave index to retrieve first and second components from the memory, and uses the quadrant value to determine the real transform coefficient value and the corresponding imaginary transform coefficient value.

4. The system of claim 1 , wherein each of the first and second single-bit analog to digital converters outputs a binary value 1 or −1, wherein each pair of binary in-phase and quadrature component samples comprises one of [1, 1] at a phase of 45 degrees, [−1, 1] at a phase of 135 degrees, [−1, −1] at a phase of 225 degrees, and [1, −1] at a phase of 315 degrees, each having a magnitude of √{square root over (2)}.

5. The system of claim 4 , wherein the complex summation value comprises a real component and an imaginary component, further comprising scaling circuitry that multiplies each of the real component and the imaginary component by √{square root over (2)}.

6. The system of claim 1 , wherein the discrete frequency transform converter determines an index into the memory for a corresponding discrete frequency transform coefficient, retrieves a real transform coefficient value and a corresponding transform coefficient imaginary value from the memory using the index, and selectively adjusts the real transform coefficient value and the imaginary transform coefficient value based on the phase value.

7. The system of claim 6 , wherein the memory stores N/4 real transform coefficient values each corresponding one of N/4 component samples, wherein the discrete frequency transform converter applies a first modulo function to the index to determine a quadrant value, applies a second modulo function to the index to determine a quarter-wave index, and uses the quarter-wave index and negated version of the quarter-wave index to retrieve first and second components from the memory.

8. The system of claim 7 , wherein the discrete frequency transform determines the real transform coefficient value and the imaginary transform coefficient value by using the retrieved first and second components retrieved from the memory for a phase value of 1, swaps the first and second components and then negates the real component for a phase of j, negates both the first and second components for a phase of −1, and swaps the first and second components and then negates the imaginary component for a phase of −j.

9. The system of claim 1 , wherein each of the first and second single-bit analog to digital converters outputs a binary value 1 or −1, wherein each pair of binary in-phase and quadrature component samples is rotated by −45 degrees to comprise one of [1, 0] at a phase of 0 degrees, [0, 1] at a phase of 90 degrees, [−1, 0] at a phase of 180 degrees, and [0, −1] at a phase of 270 degrees.

10. The system of claim 9 , wherein the complex summation value comprises a real component and an imaginary component, further comprising scaling and rotation circuitry that provides the frequency domain value by subtracting the imaginary component of the complex summation value from the real component of the complex summation value to provide a real component of the frequency domain value, and by adding the real and imaginary components of the complex summation value to provide an imaginary component of the frequency domain value.

11. The method of claim 1 , further comprising determining an index into the memory for a corresponding discrete frequency transform coefficient, retrieving a real transform coefficient value and a corresponding transform coefficient imaginary value from the memory using the index, and selectively adjusting the real transform coefficient value and the imaginary transform coefficient value based on the phase value.

12. The method of claim 11 , wherein the storing comprising storing N/4 real transform coefficient values each corresponding one of N/4 component samples, further comprising applying a first modulo function to the index for determining a quadrant value, applying a second modulo function to the index for determining a quarter-wave index, and using the quarter-wave index and negated version of the quarter-wave index for retrieving first and second components from the memory.

13. The method of claim 12 , further comprising determining the real transform coefficient value and the imaginary transform coefficient value by using the retrieved first and second components retrieved from the memory for a phase value of 1, swapping the first and second components and then negating the real component for a phase of j, negating both the first and second components for a phase of −1, and swapping the first and second components and then negates the imaginary component for a phase of −j.

14. A method of performing discrete frequency transform, comprising:
converting an analog input signal into N pairs of binary in-phase and quadrature component samples, wherein N is a predetermined number of samples and wherein each of the N pairs of binary in-phase and quadrature phase component samples comprises one of four values with a corresponding one of four phases;
determining a phase value for each of the N pairs of binary in-phase and quadrature phase component samples;
storing a plurality of discrete frequency transform coefficient values based on N;
using a corresponding phase value and a corresponding pair of discrete frequency transform coefficient values retrieved from the memory for a selected frequency bin for determining a corresponding discrete frequency component for each of the N pairs of binary in-phase and quadrature phase component samples; and
summing the corresponding N fr

Assignees

• Silicon Lab Inc

Inventors

• Verma Anant

Classifications

• G06F17/14

  Fourier, Walsh or analogous domain transformations {, e.g. Laplace, Hilbert, Karhunen-Loeve, transforms (for correlation function computation G06F17/156; spectrum analysers G01R23/16)} · CPC title

• G06F7/523

  Multiplying only · CPC title

• H03M1/1085 Primary

  using domain transforms, e.g. Fast Fourier Transform · CPC title

• G06F7/49

  Computations with a radix, other than binary, 8, 16 or decimal, e.g. ternary, negative or imaginary radices, mixed radix {non-linear PCM (G06F7/4824 takes precedence)} · CPC title

• H04L27/2651 Primary

  Modification of fast Fourier transform [FFT] or discrete Fourier transform [DFT] demodulators for performance improvement · CPC title