Protection devices with trigger devices and methods of formation thereof

Patent metadata

Field	Value
Publication number	US-11600615-B2
Application number	US-202016919833-A
Country	US
Kind code	B2
Filing date	Jul 2, 2020
Priority date	Apr 13, 2015
Publication date	Mar 7, 2023
Grant date	Mar 7, 2023

Abstract

A method of forming a semiconductor device includes forming a first vertical protection device comprising a thyristor in a substrate, forming a first lateral trigger element for triggering the first vertical protection device in the substrate, and forming an electrical path in the substrate to electrically couple the first lateral trigger element with the first vertical protection device.

First claim

What is claimed is:

1. A method of forming an electrostatic discharge protection device, the method comprising:
forming a first vertical protection device comprising a thyristor in a substrate, the thyristor comprising a first terminal at an upper major surface of the substrate and a second terminal at a lower major surface of the substrate;
forming a first lateral trigger element for triggering the first vertical protection device in the substrate, the first lateral trigger element being coupled to the first terminal of the thyristor and configured to cause a current to flow from the first terminal to the second terminal in response to a voltage across the first lateral trigger element exceeding a threshold voltage; and
forming a metallic conductive path in the substrate to electrically couple the first lateral trigger element with the second terminal of the thyristor,
wherein the substrate comprises an underlying region extending to the lower major surface of and forming the second terminal of the thyristor, and
wherein the underlying region extends continuously along the lower major surface from a location that is directly underneath the first terminal to a location wherein the metallic conductive path extends into the underlying region.

2. The method of claim 1 , further comprising: forming a doped sinker region connecting two regions of the substrate.

3. The method of claim 1 , wherein forming the metallic conductive path in the substrate comprises:
forming a first opening extending into the substrate; and
filling the first opening with a first metallic conduction layer, wherein the first metallic conduction layer electrically couples the first lateral trigger element with the first vertical protection device.

4. The method of claim 3 , wherein the first metallic conduction layer is disposed along sidewalls of the first opening.

5. The method of claim 4 , further comprising filling a fill material disposed over the first metallic conduction layer in the first opening.

6. The method of claim 3 , further comprising forming an insulating sidewall spacer on sidewalls of the first opening, wherein the first metallic conduction layer is insulated from sidewalls of the first opening by the insulating sidewall spacer.

7. The method of claim 3 , further comprising forming a counter-doped region lining sidewalls of the first opening.

8. The method of claim 3 , further comprising:
forming a second opening extending into the substrate; and
filling the second opening with a second metallic conduction layer, wherein the first vertical protection device is coupled to a first contact pad disposed over a major surface of the substrate, and wherein the second metallic conduction layer electrically couples the first vertical protection device with a second contact pad disposed over the major surface of the substrate.

9. A method of forming an electrostatic discharge protection device, the method comprising:
forming a vertical protection device in a semiconductor substrate, the semiconductor substrate comprising an upper region comprising a plurality of doped regions and an upper major surface of the semiconductor substrate, and an underlying region comprising a lower major surface of the semiconductor substrate, wherein the vertical protection device comprises a first terminal comprising a first doped region of the plurality of doped regions, the first doped region being contiguous with the upper major surface, and a second terminal comprising a second doped region in the underlying region;
forming a lateral trigger element in the semiconductor substrate, the lateral trigger element sharing the first doped region with the vertical protection device and extending laterally to a third doped region contiguous with the upper major surface, the lateral trigger element being configured to cause a current to flow from the first terminal to the second terminal in response to a voltage across the lateral trigger element exceeding a threshold voltage; and
forming a metal interconnect in an opening in the upper major surface of the semiconductor substrate, the metal interconnect extending from the upper major surface into the underlying region and comprising a first end coupled to the third doped region of the lateral trigger element, and a second end directly coupled to the second doped region of the vertical protection device,
wherein the underlying region extends continuously along the lower major surface from a location that is directly underneath the first terminal to a location wherein the metal interconnect extends into the underlying region.

10. The method of claim 9 , wherein forming the metal interconnect in the opening comprises:
forming the opening in the upper major surface extending into the semiconductor substrate;
forming an insulating sidewall spacer on sidewalls of the opening; and
filling the opening with a metallic conduction layer, the metallic conduction layer electrically coupling the lateral trigger element with the vertical protection device, the metallic conductive layer being insulated from the sidewalls of the opening by the insulating sidewall spacer.

11. The method of claim 9 , wherein forming the metal interconnect in the opening comprises:
forming the opening in the upper major surface extending into the semiconductor substrate; and
filling the opening with a metallic conduction layer, the metallic conduction layer being disposed along sidewalls of the opening and electrically coupling the lateral trigger element with the vertical protection device.

12. The method of claim 9 , wherein forming the metal interconnect in the opening comprises:
forming the opening in the upper major surface extending into the semiconductor substrate and through the first doped region and the underlying region to the lower major surface of the semiconductor substrate;
filling the opening with a metallic conduction layer, the metallic conduction layer electrically coupling the lateral trigger element with the vertical protection device; and
forming a back side metal layer under the lower major surface.

13. A method of forming an electrostatic discharge protection device, the method comprising:
forming a second doped region having a second doping type over a first doped region of a semiconductor substrate, the first doped region having a first doping type that is opposite the second doping type, wherein the second doped region comprises an upper major surface of the semiconductor substrate;
forming a third doped region having the first doping type in the second doped region;
forming a fourth doped region having the second doping type in the third doped region to form a first current path of a vertical protection device flowing from the upper major surface through the fourth, third, and second doped regions to the first doped region;
forming a fifth doped region having the second doping type in the third doped region and physically contacting the second doped region to form a second current path of a lateral trigger device flowing from the fourth doped region to the fifth doped region, the lateral trigger device being configured to cause a current to flow between the first doped region and the fourth doped region in response to a voltage across the lateral trigger device exceeding a threshold voltage; and
forming a metallic interconnect in an opening on the upper major surface of the semiconductor substrate, the opening extending from the upper major surface through the second doped region and into the first doped region, wherein the metallic interconnect couples the fifth doped region to the first doped region,
wherein the substrate comprises an u

Assignees

• Infineon Technologies Ag

Inventors

• Vendt Vadim Valentinovic
• Willemen Joost Adriaan
• Schmenn Andre
• Sojka Damian

Classifications

• H10D18/00

  Thyristors · CPC title

• H10D84/403

  Combinations of FETs or IGBTs with BJTs and with one or more of diodes, resistors or capacitors · CPC title

• H10D89/611

  using diodes as protective elements · CPC title

• H10D89/713 Primary

  including a PNP transistor and a NPN transistor, wherein each of said transistors has its base region coupled to the collector region of the other transistor, e.g. silicon controlled rectifier [SCR] devices · CPC title

• H10D89/711

  using bipolar transistors as protective elements · CPC title