Level shifter, gate driving circuit, and display device

Patent metadata

Field	Value
Publication number	US-11600213-B2
Application number	US-202117542583-A
Country	US
Kind code	B2
Filing date	Dec 6, 2021
Priority date	Dec 24, 2020
Publication date	Mar 7, 2023
Grant date	Mar 7, 2023

Abstract

A display device includes a level shifter and a gate driving circuit that can reduce differences in characteristics among gate signals to improve image quality by controlling a signal waveform of a first clock signal of the m number of clock signals different from a signal waveform of an m-th clock signal when m number of gate signals is output by using m number of clock signals.

First claim

What is claimed is:

1. A display device comprising:
a substrate;
m number of gate lines disposed over the substrate where m is a natural number of 2 or more; and
a gate driving circuit disposed over the substrate and configured to supply m number of gate signals based on m number of clock signals to the m number of gate lines,
wherein the gate driving circuit comprises m number of output buffer circuits configured to output the m number of gate signals based on the m number of clock signals, and a control circuit configured to control the m number of output buffer circuits,
wherein each of the m number of output buffer circuits comprises a pull-up transistor and a pull-down transistor, and a point at which the pull-up transistor and the pull-down transistor are connected is electrically connected with a corresponding gate line among the m number of gate lines,
wherein all gate nodes of the pull-up transistors included in the m number of output buffer circuits are electrically connected with one another, and all gate nodes of the pull-down transistors included in the m number of output buffer circuits are electrically connected with one another, and
wherein a signal waveform of at least one of the m number of clock signals is different from at least one signal waveforms of at least one other clock signals of the m number of clock signals.

2. The display device according to claim 1 , wherein the m number of gate signals comprises a first gate signal having a turn-on level voltage duration at the earliest timing and an m-th gate signal having a turn-on level voltage duration at the latest timing,
wherein the m number of clock signals comprises a first clock signal corresponding to the first gate signal, and an m-th clock signal corresponding to the m-th gate signal, and
wherein a falling length of the first clock signal is greater than a falling length of the m-th clock signal.

3. The display device according to claim 2 , wherein a difference between a falling length of the first gate signal and a falling length of the m-th gate signal is smaller than a difference between the falling length of the first clock signal and the falling length of the m-th clock signal.

4. The display device according to claim 1 , wherein the m number of gate signals comprises a first gate signal having a turn-on level voltage duration at an earliest timing and an m-th gate signal having a turn-on level voltage duration at a latest timing,
wherein the m number of clock signals comprises a first clock signal corresponding to the first gate signal, and an m-th clock signal corresponding to the m-th gate signal, and
wherein a rising length of the m-th clock signal is greater than a rising length of the first clock signal.

5. The display device according to claim 4 , wherein a difference between a rising length of the first gate signal and a rising length of the m-th gate signal is smaller than a difference between the rising length of the first clock signal and the rising length of the m-th clock signal.

6. The display device according to claim 1 , wherein, when the m is 2, the m number of clock signals comprises a first clock signal and a second clock signal, and the m number of gate signals comprises a first gate signal and a second gate signal,
wherein the gate driving circuit is capable of outputting the first gate signal to a first gate line according to the first clock signal, and outputting the second gate signal to a second gate line according to the second clock signal,
wherein a turn-on level voltage duration of the first gate signal and a turn-on level voltage duration of the second gate signal overlap, and the turn-on level voltage duration of the first gate signal is placed at a timing earlier than that of the second gate signal, and
wherein a falling length of the first clock signal is greater than a falling length of the second clock signal, or a rising length of the second clock signal is greater than a rising length of the first clock signal.

7. The display device according to claim 6 , wherein the gate driving circuit comprising:
a first output buffer circuit configured to output the first gate signal to the first gate line through a first gate output terminal in response to the first clock signal input to a first clock input terminal;
a second output buffer circuit configured to output the second gate signal to the second gate line through a second gate output terminal in response to the second clock signal input to a second clock input terminal; and
a control circuit configured to control the first output buffer circuit and the second output buffer circuit,
wherein the first output buffer circuit comprises a first pull-up transistor electrically connected between the first clock input terminal and the first gate output terminal and controlled by a voltage at a Q node, and a first pull-down transistor electrically connected between the first gate output terminal and a base input terminal to which a base voltage is input, and controlled by a voltage at a QB node, and
wherein the second output buffer circuit comprises a second pull-up transistor electrically connected between the second clock input terminal and the second gate output terminal and controlled by the voltage at the Q node, and a second pull-down transistor electrically connected between the second gate output terminal and the base input terminal, and controlled by the voltage at the QB node.

8. The display device according to claim 7 , wherein the first output buffer circuit further comprises a first additional pull-down transistor electrically connected between the first gate output terminal and the base input terminal, and controlled by a voltage at another QB node different from the QB node,
wherein the second output buffer circuit further comprises a second additional pull-down transistor electrically connected between the second gate output terminal and the base input terminal, and controlled by the voltage at the another QB node, and
wherein the first pull-down transistor and the first additional pull-down transistor operate alternately, and the second pull-down transistor and the second additional pull-down transistor operate alternately.

9. The display device according to claim 6 , further comprising a level shifter configured to output the first clock signal and the second clock signal to the gate driving circuit,
wherein the level shifter comprises:
a first clock output buffer for generating the first clock signal and outputting the generated first clock signal to the first clock output terminal; and
a second clock output buffer for generating the second clock signal and outputting the generated second clock signal to the second clock output terminal,
wherein the first clock output buffer comprises a first rising control circuit including N number of first rising control transistors electrically connected between a high level voltage node and the first clock output terminal where N is a natural number of 2 or more, and a first falling control circuit including N number of first falling control transistors electrically connected between a low level voltage node and the first clock output terminal,
wherein the second clock output buffer comprises a second rising control circuit including N number of second rising control transistors electrically connected between the high level voltage node and the second clock output terminal, where a second falling control circuit including N number of second falling control transistors electrically connected between the low level voltage node and the second clock output terminal, and
wherein respective turn-ons and turn-offs of N number of control transistors included in at least one of the first rising control circ

Assignees

• Lg Display Co Ltd

Inventors

• Hwang Sujin
• Son Miyoung
• Kim Eungkyu
• Shin Hongjae
• Chang Minkyu

Classifications

• B64C39/024

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• G09G2310/0243

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• G09G2310/0289

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• G09G3/3233 Primary

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