Cache memory architecture and management

Patent metadata

Field	Value
Publication number	US-11599461-B2
Application number	US-202117385257-A
Country	US
Kind code	B2
Filing date	Jul 26, 2021
Priority date	Jul 26, 2021
Publication date	Mar 7, 2023
Grant date	Mar 7, 2023

Abstract

Aspects of the present disclosure relate to data cache management. In embodiments, a storage array's memory is provisioned with cache memory, wherein the cache memory includes one or more sets of distinctly sized cache slots. Additionally, a logical storage volume (LSV) is established with at least one logical block address (LBA) group. Further, at least one of the LSV's LBA groups is associated with two or more distinctly sized cache slots based on an input/output (IO) workload received by the storage array.

First claim

The invention claimed is:

1. A method comprising:
provisioning a storage array's memory with cache memory, wherein the cache memory includes one or more sets of distinctly sized cache slots;
establishing a logical storage volume (LSV) with at least one logical block address (LBA) group; and
associating at least one of the LSV's LBA groups with two or more distinctly sized cache slots based on an input/output (IO) workload received by the storage array.

2. The method of claim 1 further comprising:
generating an initial storage array resource profile based on the storage array's intended use characteristics; and
provisioning the cache memory with the one or more sets of distinctly sized cache slots using the initial storage array resource profile.

3. The method of claim 1 further comprising establishing one or more cache slot pools.

4. The method of claim 3 further comprising:
determining each of the cache slot's attributes; and
establishing the one or more cache slot pools based on one or more of the determined cache slot attributes and current/historical IO workloads received by the storage array.

5. The method of claim 4 , wherein the cache slot attributes relate one or more of each cache slot's size, performance capability, resiliency, memory type, and other related cache memory metrics.

6. The method of claim 1 further comprising:
monitoring each IO workload received by the storage array; and
analyzing each IO workload's IO request characteristics.

7. The method of claim 6 further comprising:
identifying one or more IO workload patterns or each IO workload's IO request patterns based on the analyzed IO request characteristics; and
establishing one or more IO workload models based on the identified patterns.

8. The method of claim 7 , wherein the two or more distinctly sized cache slots having a memory type including a volatile cache memory or a persistent cache memory.

9. The method of claim 8 further comprising:
establishing one or more cache slot pools based on predicted IO request characteristics defined by the one or more IO workload models and each cache slot's memory type.

10. The method of claim 9 further comprising:
provisioning at least one of the LSV's LBA groups with one or more distinctly sized cache slots and distinct memory types based on the predicted IO request characteristics.

11. An apparatus comprising a memory and processor configured to:
provision a storage array's memory with cache memory, wherein the cache memory includes one or more sets of distinctly sized cache slots;
establish a logical storage volume (LSV) with at least one logical block address (LBA) group; and
associate at least one of the LSV's LBA groups with two or more distinctly sized cache slots based on an input/output (JO) workload received by the storage array.

12. The apparatus of claim 11 further configured to:
generate an initial storage array resource profile based on the storage array's intended use characteristics; and
provision the cache memory with the one or more sets of distinctly sized cache slots using the initial storage array resource profile.

13. The apparatus of claim 11 further configured to:
establish one or more cache slot pools.

14. The apparatus of claim 13 further configured to:
determine each of the cache slot's attributes; and
establish the one or more cache slot pools based on one or more of the determined cache slot attributes and current/historical IO workloads received by the storage array.

15. The apparatus of claim 14 , wherein the cache slot attributes relate one or more of each cache slot's size, performance capability, resiliency, memory type, and other related cache memory metrics.

16. The apparatus of claim 11 further configured to:
monitor each IO workload received by the storage array; and
analyze each IO workload's IO request characteristics.

17. The apparatus of claim 16 further configured to:
identify one or more IO workload patterns or each IO workload's IO request patterns based on the analyzed IO request characteristics; and
establish one or more IO workload models based on the identified patterns.

18. The apparatus of claim 17 , wherein the two or more distinctly sized cache slots have a memory type, including a volatile cache memory or a persistent cache memory.

19. The apparatus of claim 18 further configured to:
establish one or more cache slot pools based on predicted IO request characteristics defined by the one or more IO workload models and each cache slot's memory type.

20. The apparatus of claim 19 further configured to:
provision at least one of the LSV's LBA groups with one or more distinctly sized cache slots and distinct memory types based on the predicted IO request characteristics.

Assignees

• Emc Ip Holding Co Llc

Inventors

• Scharland Michael
• Halstead Mark
• Yu Rong
• Wu Peng
• Yoder Benjamin
• Sahasrabudhe Kaustubh

Classifications

• G06F2212/261

  Storage comprising a plurality of storage devices · CPC title

• G06F12/0873

  Mapping of cache memory to specific storage devices or parts thereof · CPC title

• G06F12/0842

  for multiprocessing or multitasking · CPC title

• G06F3/0689

  Disk arrays, e.g. RAID, JBOD · CPC title

• G06F3/0688

  Non-volatile semiconductor memory arrays · CPC title