Test apparatus and test method to a memory device

Patent metadata

Field	Value
Publication number	US-11598806-B2
Application number	US-202117155043-A
Country	US
Kind code	B2
Filing date	Jan 21, 2021
Priority date	Jan 21, 2021
Publication date	Mar 7, 2023
Grant date	Mar 7, 2023

Abstract

A test system is disclosed. The test system includes a tester, a first voltage stabilization circuit, and a device under test (DUT). The tester generates a first operational voltage and a control signal. The first voltage stabilization circuit transmits a second operational voltage, associated with the first operational voltage, to a socket board. The DUT operates with the second operational voltage received through the socket board. The first voltage stabilization circuit is further configured to control, according to the control signal, the second operational voltage to have a first voltage level when the DUT is operating.

First claim

What is claimed is:

1. A test system, comprising:
a tester configured to generate a first operational voltage and a control signal;
a first voltage stabilization circuit configured to transmit a second operational voltage, associated with the first operational voltage, to a socket board; and
a device under test (DUT) configured to operate with the second operational voltage received through the socket board,
wherein the first voltage stabilization circuit comprises:
a comparison circuit configured to compare the second operational voltage with an initial voltage indicated by the control signal, and to generate a feedback signal; and
an adjustment circuit configured to pull up, according to the feedback signal, the voltage level of the second operational voltage to a first voltage level when the DUT is operating.

2. The test system of claim 1 , wherein the first voltage level equals to a voltage level of the first operation voltage.

3. The test system of claim 1 , further comprising:
a test interface board electrically coupled to the tester, wherein the first voltage stabilization circuit and the socket board are integrated in the test interface board.

4. The test system of claim 1 , further comprising:
a plurality of first power supplies configured to generate the first operational voltage to the first voltage stabilization circuit;
a second voltage stabilization circuit configured to transmit a third operational voltage to the DUT through the socket board; and
a plurality of second power supplies configured to generate a fourth operational voltage to the second voltage stabilization circuit for generating the third operational voltage.

5. The test system of claim 4 , wherein the second voltage stabilization circuit comprises:
an adjustment circuit configured to adjust a voltage level of the third operational voltage to a second voltage level which equals to the fourth operational voltage.

6. The test system of claim 1 , further comprising:
a second voltage stabilization circuit configured to transmit a third operational voltage, associated with a fourth operational voltage received by the second voltage stabilization circuit, to the socket board, and configured to control a voltage level of the third operational voltage to be the same as the fourth operational voltage.

7. The test system of claim 1 , wherein the DUT is a low power double data rate memory (LPDDR) device.

8. A test method, comprising:
operating a device under test (DUT) with a first operational voltage;
comparing, by a first comparison circuit comprised in a first voltage stabilization circuit, a voltage level of the first operational voltage with a voltage level of a first initial voltage;
when the voltage level of the first operational voltage is different from the first initial voltage, adjusting, by a first adjustment circuit comprised in the first voltage stabilization circuit, the voltage level of the first operational voltage to the voltage level of the first initial voltage,
generating, by the first comparison circuit, a feedback signal in response to the comparison, to the adjustment circuit; and
pulling up, by the first adjustment circuit, the voltage level of the first operational voltage.

9. The test method of claim 8 , further comprising:
generating, by at least one power supply, a second operational voltage to a voltage stabilization circuit for generating the first operational voltage, wherein a voltage level of the second operational voltage equals to the first initial voltage.

10. The test method of claim 8 , further comprising:
operating the DUT with a second operational voltage different from the first operation voltage; and
controlling, by a voltage stabilization circuit, a voltage level of the second operational voltage to equal to a second initial voltage,
wherein the second initial voltage is provided by a tester to the voltage stabilization circuit.

11. The test method of claim 8 , further comprising:
operating the DUT with a second operational voltage;
comparing, by a second comparison circuit, a voltage level of the second operational voltage with a second initial voltage different from the first initial voltage; and
in response to the comparison, adjusting, by a second adjustment circuit, the voltage level of the second operational to have the second initial voltage.

12. The test method of claim 8 , wherein adjusting the voltage level of the first operational voltage comprises:
when the voltage level of the first operational voltage is smaller than the first initial voltage, pulling up, by the first adjustment circuit, the voltage level of the first operational voltage.

Assignees

• Nanya Technology Corp

Inventors

• Tseng Yu-Wei
• Chang Chih-Ming
• Fang Wan-Chun
• Hsu Jui-Chung
• Li Chun-Hsi

Classifications

• G01R31/3172

  Optimisation aspects, e.g. using functional pin as test pin, pin multiplexing · CPC title

• G01R31/3004

  Current or voltage test · CPC title

• G11C29/56

  External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor · CPC title

• G11C29/56004

  Pattern generation · CPC title

• G11C2029/5602

  Interface to device under test · CPC title