Adaptive equalization using correlation of data patterns with errors

Patent metadata

Field	Value
Publication number	US-11595235-B2
Application number	US-202117363132-A
Country	US
Kind code	B2
Filing date	Jun 30, 2021
Priority date	Apr 27, 2006
Publication date	Feb 28, 2023
Grant date	Feb 28, 2023

Abstract

An integrated receiver supports adaptive receive equalization. An incoming bit stream is sampled using edge and data clock signals derived from a reference clock signal. A phase detector determines whether the edge and data clock signals are in phase with the incoming data, while some clock recovery circuitry adjusts the edge and data clock signals as required to match their phases to the incoming data. The receiver employs the edge and data samples used to recover the edge and data clock signals to note the locations of zero crossings for one or more selected data patterns. The pattern or patterns may be selected from among those apt to produce the greatest timing error. Equalization settings may then be adjusted to align the zero crossings of the selected data patterns with the recovered edge clock signal.

First claim

What is claimed is:

1. A receiver comprising:
a receive port to receive an input signal expressing a series of input symbols;
an equalizer coupled to the receive port to equalize the input signal, responsive to an equalizer control signal, to thereby create an equalized signal expressing a series of equalized symbols;
a data sampler to produce a series of data samples from the series of equalized symbols;
a phase detector coupled to the data sampler to issue a phase-error signal responsive to the data samples;
a mask circuit coupled to the data sampler to assert a match signal responsive to a pattern of the data samples; and
equalization logic to update the equalizer control signal responsive to the phase-error signal and the match signal.

2. The receiver of claim 1 , further comprising an edge sampler to produce a series of edge samples from the series of equalized symbols, the phase detector to issue the phase-error signal responsive to the data samples and the edge samples.

3. The receiver of claim 2 , further comprising clock-recovery circuitry coupled to the data sampler and the edge sampler, the clock-recovery circuitry to time the data sampler and the edge sampler responsive to the data samples and the edge samples.

4. The receiver of claim 2 , wherein the phase-error signal comprises at least one of an early signal and a late signal.

5. The receiver of claim 1 , wherein the mask circuit comprises:
a pattern register to store the pattern;
a data register to store the series of data samples; and
pattern-matching logic coupled to the pattern register and the data register to assert the match signal responsive to a match between the pattern and the data samples.

6. The receiver of claim 1 , wherein the pattern of the data samples represents a high-frequency component of the input signal.

7. The receiver of claim 6 , the mask circuit to assert the match signal responsive to a second pattern of the data samples.

8. The receiver of claim 7 , wherein the second pattern represents a lower-frequency component of the input signal.

9. The receiver of claim 8 , wherein the equalization logic adjusts the equalizer control signal responsive to a ratio of errors correlated with the high-frequency component to errors correlated with the lower-frequency component.

10. The receiver of claim 1 , further comprising:
a second data sampler to produce a second series of data samples from the series of equalized symbols;
the mask circuit coupled to the second data sampler to assert the match signal responsive to a second pattern of the second data samples.

11. A method comprising:
equalizing an input signal expressing a series of symbols to create an equalized signal, the equalizing responsive to an equalization setting;
sampling the equalized signal to produce a series of data samples;
issuing a phase-error signal responsive to the data samples;
asserting a match signal responsive to a pattern of the data samples; and
adjusting the equalization setting responsive to the phase-error signal and the match signal.

12. The method of claim 11 , further comprising sampling the equalized signal to produce a series of edge samples and issuing the phase-error signal responsive to the data samples and the edge samples.

13. The method of claim 12 , further comprising sampling the equalized signal responsive to a clock signal and phase adjusting the clock signal responsive to the data samples and the edge samples.

14. The method of claim 12 , wherein the phase-error signal comprises at least one of an early signal and a late signal.

15. The method of claim 11 , further comprising:
storing a pattern; and
asserting the match signal responsive to a match between the pattern and the data samples.

16. The method of claim 11 , wherein the pattern of the data samples represents a high-frequency component of the input signal.

17. The method of claim 16 , further comprising asserting the match signal responsive to a second pattern of the data samples.

18. The method of claim 17 , wherein the second pattern represents a lower-frequency component of the input signal.

19. The method of claim 18 , further comprising adjusting the equalization setting responsive to a ratio of errors correlated with the high-frequency component to errors correlated with the lower-frequency component.

Assignees

• Rambus Inc

Inventors

• Palmer Robert E

Classifications

• H04L7/046

  using a dotting sequence · CPC title

• H04L25/069

  by detecting edges or zero crossings · CPC title

• H04L7/041 Primary

  using special codes as synchronising signal · CPC title

• H04L25/03006

  Arrangements for removing intersymbol interference · CPC title

• H04L25/03273

  with carrier recovery circuitry · CPC title