Network-centric architecture and algorithms to accelerate distributed training of neural networks
US-2021374503-A1 · Dec 2, 2021 · US
US11595062B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-11595062-B2 |
| Application number | US-202017130538-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 22, 2020 |
| Priority date | May 24, 2019 |
| Publication date | Feb 28, 2023 |
| Grant date | Feb 28, 2023 |
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A decompression apparatus is provided. The decompression apparatus includes a memory configured to store compressed data decompressed and used in neural network processing of an artificial intelligence model, a decoder configured to include a plurality of logic circuits related to a compression method of the compressed data, decompress the compressed data through the plurality of logic circuits based on an input of the compressed data, and output the decompressed data, and a processor configured to obtain data of a neural network processible form from the data output from the decoder.
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What is claimed is: 1. A decompression apparatus comprising: a memory configured to store: compressed data, the compressed data configured to be decompressed and used in neural network processing of an artificial intelligence model, and a patch information corresponding to the compressed data; a decoder comprising a plurality of logic circuits related to a compression method of the compressed data, the decoder being configured to: decompress the compressed data through the plurality of logic circuits based on an input of the compressed data, and output the decompressed data; and a processor configured to change some binary data values of a plurality of elements included in the decompressed data output from the decoder based on the patch information and obtain data of a neural network processible form from the decompressed data, wherein the patch information comprises error information generated in a process of obtaining the compressed data. 2. The decompression apparatus of claim 1 , wherein the memory is further configured to store a representative value matrix corresponding to the compressed data, wherein the processor is further configured to: obtain the data of the neural network processible form based on the decompressed data and the representative value matrix, and perform the neural network processing using the data of the neural network processible form, and wherein the decompressed data and the representative value matrix comprise matrices obtained by quantizing an original matrix included in the artificial intelligence model. 3. The decompression apparatus of claim 2 , wherein the memory is further configured to store a pruning index matrix corresponding to the compressed data, wherein the processor is further configured to update the decompressed data based on the pruning index matrix, wherein the pruning index matrix comprises a matrix obtained in a pruning process of the original matrix, and wherein the pruning index matrix is used in a process of obtaining the compressed data. 4. The decompression apparatus of claim 2 , wherein the memory is further configured to: store a first pruning index matrix corresponding to the compressed data, and store a second pruning index matrix corresponding to the compressed data, wherein the processor is further configured to: obtain a pruning index matrix based on the first pruning index matrix and the second pruning index matrix, and update the decompressed data based on the pruning index matrix, wherein the pruning index matrix comprises a matrix obtained in a pruning process of the original matrix, wherein the pruning index matrix is used in a process of obtaining the compressed data, and wherein the first pruning index matrix and the second pruning index matrix are obtained based on each of a first sub-matrix and a second sub-matrix obtained by factorizing the original matrix. 5. The decompression apparatus of claim 2 , wherein the decompressed data comprises a matrix obtained by interleaving the original matrix and then quantizing the interleaved matrix, and wherein the processor is further configured to: de-interleave the data of the neural network processible form according to a manner corresponding to the interleaving, and perform the neural network processing using the de-interleaved data. 6. The decompression apparatus of claim 2 , wherein the processor comprises a plurality of processing elements arranged in a matrix form, and wherein the processor is further configured to perform the neural network processing using the plurality of processing elements. 7. The decompression apparatus of claim 2 , wherein the decompressed data comprises a matrix obtained by dividing the original matrix into a plurality of matrices each having a same number of columns and rows and quantizing one of the plurality of matrices. 8. The decompression apparatus of claim 2 , wherein the original matrix comprises a matrix obtained after a learning process of the artificial intelligence model is completed. 9. The decompression apparatus of claim 2 , wherein the original matrix is in a non-compressed state. 10. The decompression apparatus of claim 1 , wherein the memory is further configured to store other compressed data configured to be decompressed and used in the neural network processing of the artificial intelligence model, wherein the decompression apparatus further comprises another decoder configured to: include a plurality of other logic circuits related to a compression method of the other compressed data, decompress the other compressed data through the plurality of other logic circuits based on an input of the other compressed data, and output the decompressed other data, and wherein the processor is further configured to: obtain other data of a neural network processible form from the decompressed other data output from the other decoder, and obtain a matrix in which each element includes a plurality of binary data by coupling the neural network processible data and the other data of the neural network processible form. 11. The decompression apparatus of claim 1 , wherein the decompression apparatus is implemented as one chip. 12. A control method of a decompression apparatus comprising a plurality of logic circuits related to a compression method of compressed data, the control method comprising: receiving, by the plurality of logic circuits, the compressed data, the compressed data configured to be decompressed and used in neural network processing of an artificial intelligence model; decompressing, by the plurality of logic circuits, the compressed data; outputting the decompressed data; changing some binary data values of a plurality of elements included in the decompressed data output from the plurality of logic circuits based on a patch information corresponding to the compressed data; and obtaining data of a neural network processible form from the decompressed data, wherein the patch information comprises error information generated in a process of obtaining the compressed data. 13. The control method of claim 12 , further comprising: obtaining the data of the neural network processible form based on the decompressed data and a representative value matrix corresponding to the compressed data; and performing the neural network processing using the data of the neural network processible form, wherein the decompressed data and the representative value matrix comprise matrices obtained by quantizing an original matrix included in the artificial intelligence model. 14. The control method of claim 13 , further comprising: updating the decompressed data based on a pruning index matrix corresponding to the compressed data, wherein the pruning index matrix comprises a matrix obtained in a pruning process of the original matrix, and wherein the pruning index matrix is used in a process of obtaining the compressed data. 15. The control method of claim 13 , further comprising: obtaining a pruning index matrix based on a first pruning index matrix corresponding to the compressed data and a second pruning index matrix corresponding to the compressed data; and updating the decompressed data based on the pruning index matrix, wherein the pruning index matrix comprises a matrix obtained in a pruning process of the original matrix, wherein the pruning index matrix is used in the process of obtaining the compressed data, and wherein the first pruning index matrix and the second pruning index matrix are obtained based on each of a first sub-matrix and a second sub-matrix obtained by fact
Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons · CPC title
modifying the architecture, e.g. adding, deleting or silencing nodes or connections · CPC title
using electronic means · CPC title
Backpropagation, e.g. using gradient descent · CPC title
Interleaver using block-wise interleaving, e.g. the interleaving matrix is sub-divided into sub-matrices and the permutation is performed in blocks of sub-matrices · CPC title
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