Time-to-digital converter stop time control

Patent metadata

Field	Value
Publication number	US-11595046-B2
Application number	US-202117515598-A
Country	US
Kind code	B2
Filing date	Nov 1, 2021
Priority date	Dec 26, 2018
Publication date	Feb 28, 2023
Grant date	Feb 28, 2023

Abstract

In described examples, an electronic circuit for determining a phase difference between a first clock signal and a second clock signal includes a timer circuit, circuitry for generating a selectively delayed transition of the second clock signal, and phase determination circuitry. The timer circuit produces an elapsed time between a transition of the first clock signal and the selectively delayed transition of the second clock signal. The circuitry for generating the selectively delayed transition of the second clock signal generates the selectively delayed transition in response to a random selection of a respective output from a plurality of second clock signal delay stages. The phase determination circuitry provides the phase difference in response to the elapsed time and the random selection of a respective output from a plurality of second clock signal delay stages.

First claim

What is claimed is:

1. A method, comprising:
clocking a first clocked stage and a second clocked stage using a test clock signal;
propagating a reference clock signal serially through the first and second clocked stages;
selecting a STOP signal from among outputs of the first and second clocked stages;
providing the reference clock signal to a timer as a START signal;
providing the STOP signal to the timer; and
calculating a difference between when the timer receives the START signal and when the timer receives the STOP signal using the timer; and
determining a phase delay based on the difference.

2. The method of claim 1 , wherein the clocking begins at a time corresponding to an edge of the reference clock signal preceding a leading transition of the reference clock signal, and the clocking ends at a time corresponding to a next transition of the reference clock signal.

3. The method of claim 1 , further comprising is used to generating the test clock signal using the reference clock signal.

4. The method of claim 1 , wherein the timer is a ring oscillator.

5. The method of claim 4 , further comprising propagating a signal through the ring oscillator beginning when the timer receives the START signal and ending when the timer receives the STOP signal.

6. The method of claim 4 , wherein the propagating the signal through the ring oscillator comprises propagating a leading edge of the reference clock signal through the ring oscillator.

7. The method of claim 5 , wherein the time between the beginning and the ending is determined using a rollover counter of the ring oscillator and using outputs of respective delay components of the ring oscillator.

8. The method of claim 1 , wherein the reference clock signal is generated by dividing a reference clock source signal by an integer N.

Assignees

• Texas Instruments Inc

Inventors

• Moe Marius
• Aaberge Tarjei

Classifications

• G04F10/005

  Time-to-digital converters [TDC] (analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60) · CPC title

• H03K5/14 Primary

  by the use of delay lines (H03K5/133 takes precedence) · CPC title

• H03K2005/00019

  Variable delay · CPC title

• H03K3/0315

  Ring oscillators · CPC title

• H03L7/085 Primary

  concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00) · CPC title