Fault voltage scaling on load switch current sense

Patent metadata

Field	Value
Publication number	US-11595034-B2
Application number	US-202117538547-A
Country	US
Kind code	B2
Filing date	Nov 30, 2021
Priority date	May 26, 2021
Publication date	Feb 28, 2023
Grant date	Feb 28, 2023

Abstract

A load switch includes a switch input, a switch output, a first field-effect transistor (FET), and a second FET. The switch input is adapted to be coupled to a controller output of a controller. The switch output is adapted to be coupled to a controller input of the controller. The first FET has a gate and a source. The gate of the first FET is coupled to the switch input. The second FET has a gate and a source. The gate of the second FET is coupled to the source of the first FET. The source of the second FET is coupled to the switch output.

First claim

What is claimed is:

1. A load switch, comprising:
a switch input terminal coupled to a controller output terminal;
a switch output terminal coupled to a controller input terminal
a first field-effect transistor (FET) having a first gate and a first source, wherein the first gate is coupled to the switch input terminal;
a second FET having a second gate, a second drain and a second source, wherein the second gate is coupled to the first source, and the second source is coupled to the switch output terminal;
a current sense circuit coupled to the second drain; and
a multiplexer coupled between the current sense circuit and the second drain.

2. The load switch of claim 1 , further comprising:
a charge pump coupled to the first source.

3. The load switch of claim 1 , further comprising:
a third FET having a third source and a third gate, wherein the third source is coupled to the second source and the switch output terminal.

4. The load switch of claim 1 , further comprising:
A fourth FET having a fourth gate coupled to a ground terminal.

5. The load switch of claim 1 , further comprising:
a source-follower circuit that includes a p-type FET (PFET) having a gate coupled to the first source and to the second gate.

6. The load switch of claim 1 , further comprising:
a current mirror having a current mirror output coupled to the first source.

7. A load switch, comprising:
a switch input and a switch output, wherein the switch input is coupled to a controller output terminal, and the switch output is coupled to a controller input terminal;
a first clamp circuit configured to control a voltage at the switch output responsive to a voltage at the switch input, wherein the first clamp circuit includes a first field-effect transistor (FET) coupled to the switch input, and a second FET coupled to the switch output; and
a second clamp circuit configured to control the voltage at the switch output to a threshold voltage level responsive to the voltage at the switch input transitioning below the threshold voltage level.

8. The load switch of claim 7 , further comprising:
a current sense circuit configured to provide a sense current that is proportional to a load current, wherein the current sense circuit is coupled to a drain of the second FET.

9. The load switch of claim 7 , wherein the second clamp circuit includes a third FET, and the threshold voltage level is responsive to a voltage at a gate of the third FET.

10. The load switch of claim 7 , further comprising:
a ground loss circuit configured to disconnect the switch output from the second FET responsive to a ground loss event.

11. The load switch of claim 8 , further comprising:
a source-follower circuit configured to divert a portion of the sense current to ground responsive to the voltage at the switch output exceeding the threshold voltage level.

12. The load switch of claim 8 , further comprising:
a sense path variation circuit configured to reduce a deviation between the sense current and a current flowing through the first FET.

13. A system comprising:
a controller having a controller input and a controller output;
a load switch having a switch input and a switch output, wherein the switch input is coupled to the controller output, and the switch output is coupled to the controller input, wherein the load switch includes:
a first field-effect transistor (FET) having a first gate and a first source, wherein the first gate is coupled to the switch input; and
a second FET having a second gate and a second source, wherein the second gate is coupled to the first source, and the second source is coupled to the switch output; and

a clamp circuit that is configured to control a voltage at the switch output to a threshold voltage level responsive to a voltage at the switch input transitioning below the threshold voltage level.

14. The system of claim 13 , further comprising a clamp circuit that includes the first and second FETs, wherein the clamp circuit is configured to control a voltage at the switch output responsive to a voltage at the switch input.

15. The system of claim 13 , wherein the load switch includes a ground loss circuit configured to disconnect the switch output from the second FET responsive to a ground loss event.

16. The system of claim 13 , wherein the load switch includes a source-follower circuit with a p-type FET having a gate that is connected to the first source and the second gate.

Assignees

• Texas Instruments Inc

Inventors

• Phillips Cameron Wayne
• Qu Wenchao
• Yang Tianhong
• Rahman Md Abidur

Classifications

• H03K17/04123 Primary

  in field-effect transistor switches · CPC title

• H03K17/0822 Primary

  in field-effect transistor switches · CPC title

• H03K17/693

  Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors (logic circuits H03K19/00; code converters H03M5/00, H03M7/00) · CPC title