Security circuit including dual encoder and endecryptor including the security circuit

Patent metadata

Field	Value
Publication number	US-11593527-B2
Application number	US-202017060099-A
Country	US
Kind code	B2
Filing date	Oct 1, 2020
Priority date	Feb 26, 2020
Publication date	Feb 28, 2023
Grant date	Feb 28, 2023

Abstract

A security circuit includes a decoder configured to receive input data and output a decoding signal in response to the input data, a first encoder configured to output one of first phenotypes corresponding to any one among integers in N-decimal (N is a natural number of 1 or more) as a first encoding value in response to the decoding signal, a second encoder configured to output one of second phenotypes corresponding to any one among integers in N-decimal as a second encoding value in response to the decoding signal, and a gate module circuit configured to generate output data by performing a logic operation on the first encoding value and the second encoding value.

First claim

What is claimed is:

1. A security circuit comprising:
a decoder configured to receive input data and output a decoding signal in response to the input data;
a first encoder configured to output one of first phenotypes corresponding to any one among integers in N-decimal (N is a natural number of 1 or more) as a first encoding value in response to the decoding signal;
a second encoder configured to output one of second phenotypes corresponding to any one among integers in N-decimal as a second encoding value in response to the decoding signal; and
a gate module circuit configured to generate output data by performing a logic operation on the first encoding value and the second encoding value,
wherein the first encoder comprises a plurality of row gates,
each of the first phenotypes is assigned to one of the plurality of row gates,
one of the plurality of row gates to which one of the first phenotypes is assigned outputs a first binary number having a bit value of 1,
the rest of the plurality of row gates output a second binary number having a bit value of 0, and
the first encoder outputs one of the first phenotypes as the first encoding value in response to the one of the plurality of row gates outputting the first binary number.

2. The security circuit of claim 1 , further comprising a permutation logic circuit configured to select one of a plurality of integers based on the decoding signal and output the selected integer as a decoding value to the first encoder and the second encoder.

3. The security circuit of claim 1 , further comprising:
a first permutation logic circuit configured to select a first integer among a plurality of integers based on the decoding signal and output the first integer as a first decoding value to the first encoder; and
a second permutation logic circuit configured to select a second integer among the plurality of integers based on the decoding signal and output the second integer as a second decoding value to the second encoder.

4. The security circuit of claim 1 , wherein the gate module circuit comprises an XOR gate, and
the output data is a result of an XOR operation on the first encoding value and the second encoding value by using the XOR gate.

5. The security circuit of claim 2 , wherein
each of the plurality of row gates comprises a plurality of first input terminals, and
one of the plurality of first input terminals receives the decoding value.

6. The security circuit of claim 5 , wherein the second encoder comprises a plurality of column gates,
each of the plurality of column gates comprises a plurality of second input terminals, and
one of the plurality of second input terminals receives the decoding value.

7. The security circuit of claim 1 , wherein the output data is a combination of a first portion comprising the first encoding value and a second portion comprising the second encoding value.

8. The security circuit of claim 1 , wherein the first encoding value or the second encoding value has a Hamming weight of 2.

9. The security circuit of claim 8 , wherein the first phenotypes or the second phenotypes comprise 3, 5, A, and C in hexadecimal, or 3, 6, 9, and C in hexadecimal.

10. The security circuit of claim 1 , wherein a sum of a Hamming weight of the first encoding value and a Hamming weight of the second encoding value is 3, 4, or 5.

11. A security circuit comprising:
a first permutation logic circuit configured to output a first decoding value;
a second permutation logic circuit configured to output a second decoding value;
a first encoder comprising a plurality of first row gates configured to receive the first decoding value, wherein the first encoder is assigned with first phenotypes based on a certain Hamming weight value as an output of the plurality of first row gates and is configured to output one of the first phenotypes assigned to one of the plurality of first row gates as a first encoding value in response to a binary number having a bit value of 1; and
a second encoder comprising a plurality of second row gates configured to receive the second decoding value, wherein the second encoder is assigned with second phenotypes based on a certain Hamming weight value as an output of the plurality of second row gates and is configured to output one of the second phenotypes assigned to one of the plurality of second row gates as a second encoding value in response to a binary number having a bit value of 1.

12. The security circuit of claim 11 , further comprising a gate module circuit configured to output first output data by performing an XOR operation on the first encoding value and the second encoding value.

13. The security circuit of claim 12 , wherein the gate module circuit outputs second output data by performing an XOR operation on a first inverted encoding value and a second inverted encoding value.

14. The security circuit of claim 11 , wherein the first phenotypes and the second phenotypes are preset so that input data and output data are mapped one-to-one.

15. The security circuit of claim 11 , wherein the first phenotypes or the second phenotypes are 3, 6, 9, and C in hexadecimal.

16. The security circuit of claim 11 , wherein the first phenotypes or the second phenotypes are 3, 5, A, and C in hexadecimal.

17. The security circuit of claim 11 , wherein at least one of the first phenotypes and the second phenotypes comprises a value having a Hamming weight of 2.

18. A security circuit comprising:
a decoder configured to receive input data and output a decoding signal in response to the input data;
a first encoder configured to output one of first phenotypes corresponding to any one among integers in N-decimal (N is a natural number of 1 or more) as a first encoding value in response to the decoding signal;
a second encoder configured to output one of second phenotypes corresponding to any one among integers in N-decimal as a second encoding value in response to the decoding signal; and
a gate module circuit configured to generate output data by performing a logic operation on the first encoding value and the second encoding value,
wherein the first phenotypes or the second phenotypes comprise 3, 5, A, and C in hexadecimal, or 3, 6, 9, and C in hexadecimal, and/or a sum of a Hamming weight of the first encoding value and a Hamming weight of the second encoding value is 3, 4, or 5.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Jaehyeok
• Lee Hyesoo
• Choi Hongmook
• Kang Jisu
• Kim Hyunil
• Shin Jonghoon

Classifications

• G06F21/72 Primary

  in cryptographic circuits · CPC title

• G06F21/78

  to assure secure storage of data (address-based protection against unauthorised use of memory G06F12/14; record carriers for use with machines and with at least a part designed to carry digital markings G06K19/00) · CPC title

• H04L9/0631

  Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms · CPC title

• G06F21/602

  Providing cryptographic facilities or services · CPC title

• H04L2209/34

  Encoding or coding, e.g. Huffman coding or error correction · CPC title