Memory apparatus with redundancy array

Patent metadata

Field	Value
Publication number	US-11593201-B2
Application number	US-201916685766-A
Country	US
Kind code	B2
Filing date	Nov 15, 2019
Priority date	Apr 26, 2017
Publication date	Feb 28, 2023
Grant date	Feb 28, 2023

Abstract

Apparatuses and methods for memory repair for a memory device are described. An example apparatus includes: a data input/output circuit that provides data via a plurality of data signal lines; memory cell arrays; an ECC/Parity redundancy array; and a redundancy circuit coupled to the plurality of data signal lines. The redundancy circuit includes an error correction block that generates error correction information based on the data and provides the error correction information to the ECC/Parity redundancy array. If during test it is determined that a failure is not repairable by standard redundancy including error correction code, the error correction parity array is not needed and can be redirected by a block repair circuit. The error correction circuit can now have its functionality changed to allow the error correction array to become a block repair.

First claim

What is claimed is:

1. An apparatus comprising:
a plurality of data terminals;
at least one memory cell array that includes a plurality of memory cells;
an ECC/parity redundancy array that includes a plurality of memory cells; and
a redundancy circuit configured to communicate data with the data terminals and further configured to provide the data to the at least one memory cell array and the ECC/parity redundancy array and to receive the data from the at least one memory cell array and the ECC/parity redundancy array,
wherein the redundancy circuit is configured to provide a portion of the data received from the plurality of data terminals to the ECC/parity redundancy array and further configured to receive the portion of the data from the ECC/parity redundancy array and to provide the portion of the data responsive to a first state of a control signal,
wherein the redundancy circuit is configured to provide error correction information to the ECC/parity redundancy array and further configured to receive the error correction information from the ECC/parity redundancy array responsive to a second state of the control signal that is different from the first state of the control signal,
wherein the redundancy circuit comprises a block repair circuit configured to prevent an error in the data responsive to the first state of the control signal,
wherein the block repair circuit is configured to replace a plurality of defective memory cells in a block in a test mode, and further configured to activate a block repair if a number of the defective memory cells is beyond error correction capability of the redundancy circuit, and
wherein the block repair circuit further comprises a fuse circuit configured to provide the control signal.

2. An apparatus, comprising:
a plurality of data terminals;
at least one memory cell array that includes a plurality of memory cells;
an ECC/parity redundancy array that includes a plurality of memory cells; and
a redundancy circuit configured to communicate data with the data terminals and further configured to provide the data to the at least one memory cell array and the ECC/parity redundancy array and to receive the data from the at least one memory cell array and the ECC/parity redundancy array,
wherein the redundancy circuit is configured to provide a portion of the data received from the plurality of data terminals to the ECC/parity redundancy array and further configured to receive the portion of the data from the ECC/parity redundancy array and to provide the portion of the data responsive to a first state of a control signal,
wherein the redundancy circuit is configured to provide error correction information to the ECC/parity redundancy array and further configured to receive the error correction information from the ECC/parity redundancy array responsive to a second state of the control signal that is different from the first state of the control signal,
wherein the redundancy circuit comprises an error correction block configured to provide error correction information based on the data from the data terminals and further configured to prevent an error in the data based on the error correction information responsive to the second state of the control signal,
wherein the error correction block includes an error correction information generation circuit and an error correction circuit,
wherein the error correction information generation circuit is configured to generate error correction information based on the data from the data terminals and further configured to provide the error correction information to the ECC/parity redundancy array, and
wherein the error correction circuit is configured to receive the data from the at least one memory cell array and the error correction information from the ECC/parity redundancy array, and further configured to detect one or more errors in the data based on the error correction information.

3. The apparatus of claim 2 , wherein the error correction circuit is configured to correct the one or more errors when a number of the one or more errors is within error correction capability of the error correction circuit, and wherein the error correction circuit is configured to provide an error signal when a number of the one or more errors is beyond error correction capability of the error correction circuit.

4. An apparatus comprising:
a data input/output circuit coupled between a plurality of data terminals and a plurality of data signal lines, configured to receive data from the plurality of data terminals and further configured to provide the data via the plurality of data signal lines;
at least one memory cell array that includes a plurality of memory cells; and
a redundancy circuit coupled to the data input/output circuit via the plurality of data signal lines, comprising:
a block repair circuit configured to redirect a first portion of the data from the data input/output circuit designated to a first block in a first array including a plurality of defective cells, among the at least one memory cell array, to a second block different from the first block in a second array, responsive to a control signal indicative of enabling the block repair circuit; and
an error correction block configured to correct an error in the data from the at least one memory cell array, responsive to the control signal indicative of not enabling the block repair circuit.

5. The apparatus of claim 4 wherein the block repair circuit is configured to be enabled responsive to the control signal when a number of defective cells exceeds an error correction capability of the error correction block.

6. The apparatus of claim 4 wherein the redundancy circuit further comprises a mapping circuit configured to remap data to and from the first array to the second array, the second array adjacent the first array.

7. The apparatus of claim 4 wherein the error correction block is configured to correct the error in the data retrieved from the at least one memory cell array based on error correction information stored in the second array.

8. The apparatus of claim 4 wherein the error correction block is further configured to generate error correction information for data from an input/output circuit, the error correction information to be stored in the second array and the data from the input/output circuit to be stored in the at least one memory cell array.

9. The apparatus of claim of claim 4 wherein the second array is disposed between the first array and a third array.

10. An apparatus, comprising:
a first memory cell array;
a second memory cell array;
a main amplifier coupled to the first and second memory cell arrays and configured to provide write data to the first or second memory cell array and to receive read data from the first or second memory cell array;
a data input/output circuit configured to receive write data and configured to provide read data; and
a redundancy circuit coupled to the main amplifier and the data input/output circuit and including an error correction block and a block repair circuit, the block repair circuit configured to redirect write data designated to a block in the first memory cell array to the second memory cell array when enabled, and the error correction block configured to detect and correct errors based on error correction information stored in the second memory cell array when the block repair circuit is disabled.

11. The apparatus of claim 10 wherein the block repair circuit comprises:
selection fuses configured to provide an enable signal and provide fuse signals indicative of dimensions of a block to be repaired; and
an error correction block configured to receive the enable signal p

Assignees

• Micron Technology Inc

Inventors

• Eichmeyer Seth
• Rehmeyer James
• Johnson Benjamin
• Johnson Jason

Classifications

• G11C29/44

  Indication or identification of errors, e.g. for repair · CPC title

• G11C29/52 Primary

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G11C29/76

  using address translation or modifications · CPC title

• G11C2029/0411

  Online error correction · CPC title