Server offload card with SoC and FPGA

Patent metadata

Field	Value
Publication number	US-11593138-B2
Application number	US-202016808286-A
Country	US
Kind code	B2
Filing date	Mar 3, 2020
Priority date	May 20, 2019
Publication date	Feb 28, 2023
Grant date	Feb 28, 2023

Abstract

A physical server with an offload card including a SoC (system-on-chip) and a FPGA (field programmable gate array) is disclosed. According to one set of embodiments, the SoC can be configured to offload one or more hypervisor functions from a CPU complex of the server that are suited for execution in software, and the FPGA can be configured to offload one or more hypervisor functions from the CPU complex that are suited for execution in hardware.

First claim

What is claimed is:

1. A server comprising:
a CPU (central processing unit) complex; and
an offload card including:
an SoC (system-on-chip); and
an FPGA (field programmable gate array) external and coupled to the SoC,

wherein the CPU complex is configured to execute one or more virtual machines (VMs),
wherein the SoC is configured to execute, in software, one or more first functions of a hypervisor associated with the one or more VMs, and
wherein the FPGA is configured to execute, in hardware, one or more second functions of the hypervisor associated with the one or more VMs.

2. A server comprising:
a CPU (central processing unit) complex configured to execute one or more virtual machines (VMs); and
an offload card including:
means for executing, in software, one or more first functions of a hypervisor associated with the one or more VMs; and
means for executing, in hardware, one or more second functions of the hypervisor associated with the one or more VMs.

3. A method comprising:
receiving, by a FPGA (field programmable gate array) residing on an offload card of a server, a network packet from a NIC (network interface card) of the server, wherein the network packet is received via an Ethernet interface interconnecting the FPGA and the NIC;
performing, by the FPGA in hardware, a lookup into a flow table based on a header of the network packet;
upon determining that no matching entry is found in the flow table for the header, forwarding, by the FPGA, the network packet to a SoC (system-on-chip) residing on the offload card, wherein the network packet is forwarded via an Ethernet interface interconnecting the FPGA and the SoC;
calculating, by the SoC in software, a next-hop destination for the network packet; and
updating, by the SoC in software, the flow table with a new flow entry including the next-hop destination.

4. The method of claim 3 further comprising, upon determining that a matching entry is found in the flow table:
updating, by the FPGA, the network packet based on the matching entry; and
transmitting, by the FPGA, the network packet to an external network via an external network interface of the FPGA.

5. The server of claim 1 wherein the SoC and the FPGA are communicatively coupled with each other via a PCIe (Peripheral Component Interconnect Express) interface that is internal to the offload card and via an Ethernet interface that is internal to the offload card.

6. The server of claim 5 wherein the SoC and the FPGA are further communicatively coupled with each other via a JTAG (Joint Test Action Group) interface that is internal to the offload card.

7. The server of claim 1 wherein the offload card is inserted into a mainboard of the server via a PCIe edge connector interface.

8. The server of claim 7 wherein the SoC is communicatively coupled with a baseboard management controller (BMC) of the server through the PCIe edge connector interface.

9. The server of claim 7 wherein the FPGA is communicatively coupled with the CPU complex through the PCIe edge connector interface.

10. The server of claim 1 wherein the SoC is communicatively coupled with one or more volatile memory modules resident on the offload card, the one or more volatile memory modules acting as a working memory from which the SoC can execute the one or more first functions.

11. The server of claim 1 wherein the SoC is communicatively coupled with a flash memory module resident on the offload card, the flash memory module storing program code for the one or more first functions.

12. The server of claim 1 wherein the FPGA is communicatively coupled with one or more volatile memory modules resident on the offload card, the one or more volatile memory modules acting as a working memory for the FPGA at a time of executing the one or more second functions.

13. The server of claim 1 wherein the FPGA is communicatively coupled with a flash memory module resident on the offload card, the flash memory module storing at least one configuration image for configuring the FPGA to execute the one or more second functions.

14. The server of claim 13 wherein the flash memory module stores a first configuration image corresponding to a normal operating configuration for the FPGA and a second configuration image corresponding to a failsafe operating configuration for the FPGA.

15. The server of claim 14 wherein the first configuration image is applied to the FPGA by default upon power-on of the offload card.

16. The server of claim 15 wherein the second configuration image is applied to the FPGA if an error occurs while applying the first configuration image.

17. The server of claim 1 wherein the FPGA includes a first external network interface communicatively coupled with a TOR (top-of-rack) network switch and a second external network interface communicatively coupled with a NIC (network interface card) of the server.

18. The server of claim 1 wherein the SoC is communicatively coupled with a BIOS (Basic Input/Output) flash component residing on the offload card via a security chip, the security chip being configured to verify integrity of firmware stored on the BIOS flash component.

19. The server of claim 1 wherein the one or more first functions include network control plane functions or storage control plane functions.

20. The server of claim 1 wherein the one or more second functions include network data plane functions or storage data plane functions.

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Chiou Derek
• Putnam Andrew
• Firestone Daniel
• Lavier Jack

Classifications

• G06F11/0796

  Safety measures, i.e. ensuring safe condition in the event of error, e.g. for controlling element · CPC title

• G06F9/5055

  considering software capabilities, i.e. software resources associated or available to the machine · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F2009/45579

  I/O management, e.g. providing access to device drivers or storage · CPC title

• H04L49/109

  Integrated on microchip, e.g. switch-on-chip · CPC title