Method of forming a high temperature sensor

US11590576B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11590576-B2
Application numberUS-202117356622-A
CountryUS
Kind codeB2
Filing dateJun 24, 2021
Priority dateJun 24, 2021
Publication dateFeb 28, 2023
Grant dateFeb 28, 2023

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  1. Title

    What the patent document calls the invention.

  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method of forming a high temperature sensor includes preparing a substrate having a surface from an electrically insulative material having a first coefficient of thermal expansion (CTE), preparing an electrical conductor from a metal material having a second CTE that is different from the first CTE, and creating an interface between the electrical conductor and the substrate with a CTE blending medium that is provided between the substrate and the electrical conductor. The CTE blending medium accommodates differing thermal expansion rates of the substrate and the electrical conductor at temperatures of at least 700° C.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of forming a high temperature downhole sensor comprising: preparing a substrate having an outer surface formed from an electrically insulative material having a first coefficient of thermal expansion (CTE); preparing an electrical conductor from a metal material having a second CTE that is different from the first CTE; and creating an interface between the electrical conductor and the outer surface of the substrate with a CTE blending medium that is provided between the substrate and the electrical conductor, the CTE blending medium forming a CTE flexible interface accommodating differing thermal expansion rates of the substrate and the electrical conductor at downhole temperatures of at least 700° C. 2. The method of claim 1 , wherein creating the interface includes forming a layer of a nickel-cobalt ferrous alloy on the one of the substrate and the electrical conductor. 3. The method of claim 1 , wherein creating the interface includes forming a material that is a blend of the electrically insulative material and the metal material. 4. The method of claim 1 , wherein creating the interface includes depositing the CTE blending medium onto the surface. 5. The method of claim 4 , wherein preparing the electrical conductor includes depositing layers of the electrical conductor on the CTE blending material. 6. The method of claim 5 , wherein depositing the layers includes forming the electrical conductor through an additive manufacturing process. 7. The method of claim 6 , wherein preparing the electrical conductor includes building the electrical conductor from one of an oxidation and corrosion resistant nickel-chromium alloy and Tungsten. 8. The method of claim 1 , wherein preparing the substrate includes creating the substrate layer by layer with an additive manufacturing process. 9. The method of claim 8 , wherein preparing the substrate includes depositing layer upon layer of a dielectric ceramic material to form a substantially planar surface. 10. The method of claim 9 , wherein preparing the electrical conductor includes depositing the electrical conductor onto the substantially planar surface. 11. The method of claim 9 , wherein depositing the electrical conductor onto the substantially planar surface includes forming a wire coil. 12. The method of claim 8 , wherein preparing the substrate includes depositing layer upon layer of a dielectric ceramic material forming a cylinder having an outer annular surface. 13. The method of claim 12 , wherein preparing the electrical conductor includes forming an electrically conductive wire. 14. The method of claim 13 , further comprising: winding the electrically conductive wire about the outer annular surface. 15. The method of claim 13 , wherein preparing the electrically conductive wire includes forming a conductor through one of a direct energy deposition (DED) process and an aerosol jetting process. 16. The method of claim 1 , wherein creating the interface between the electrical conductor to the substrate with the CTE blending medium includes fusing the electrical conductor to the substrate with the CTE blending medium. 17. The method of claim 1 , wherein creating the interface includes depositing the CTE blending medium onto the outer surface of the substrate. 18. The method of claim 17 , wherein creating the interface further includes depositing the layer upon layer of a dielectric ceramic material onto the CTE blending medium to form the substrate. 19. The method of claim 18 , wherein creating the interface still further includes fusing the electrical conductor to the CTE blending material. 20. A high temperature sensor formed by the method of claim 1 . 21. A high temperature sensor formed by the method of claim 1 installed on a downhole tool positionable in a wellbore at a depth having a temperature of at least 700° C.

Assignees

Inventors

Classifications

  • Temperature · CPC title

  • Formation of a green body · CPC title

  • involving the connection or repairing of preformed parts · CPC title

  • Processes of additive manufacturing · CPC title

  • B33Y80/00Primary

    Products made by additive manufacturing · CPC title

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Frequently asked questions

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What does patent US11590576B2 cover?
A method of forming a high temperature sensor includes preparing a substrate having a surface from an electrically insulative material having a first coefficient of thermal expansion (CTE), preparing an electrical conductor from a metal material having a second CTE that is different from the first CTE, and creating an interface between the electrical conductor and the substrate with a CTE blend…
Who is the assignee on this patent?
Sakthivel Navin, Avagliano Aaron, Shaikh Farhat, and 3 more
What technology area does this patent fall under?
Primary CPC classification B33Y80/00. Mapped technology areas include Operations & Transport.
When was this patent published?
Publication date Tue Feb 28 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).