Hardware clock with built-in accuracy check

Patent metadata

Field	Value
Publication number	US-11588609-B2
Application number	US-202117148605-A
Country	US
Kind code	B2
Filing date	Jan 14, 2021
Priority date	Jan 14, 2021
Publication date	Feb 21, 2023
Grant date	Feb 21, 2023

Abstract

A network device includes one or more ports for connecting to a communication network, packet processing circuitry and clock circuitry. The packet processing circuitry is configured to communicate packets over the communication network via the ports. The clock circuitry includes a hardware clock configured to indicate a network time used for synchronizing network devices in the communication network, and a built-in accuracy test circuit configured to check an accuracy of the hardware clock.

First claim

The invention claimed is:

1. A network device, comprising:
one or more ports for connecting to a communication network;
packet processing circuitry configured to communicate packets over the communication network via the ports; and
clock circuitry, comprising:
a hardware clock configured to output a digital word indicative of a network time used for synchronizing the network device to one or more other network devices in the communication network; and
a built-in accuracy test circuit configured to receive an external reference signal having a predefined pattern of rising and/or falling edges and sample the digital word, which is output by the hardware clock, at a timing that is derived from the external reference signal.

2. The network device according to claim 1 , wherein the hardware clock is configured to track the network time in accordance with a Precision Time Protocol (PTP).

3. The network device according to claim 1 , wherein the built-in accuracy test circuit is configured to transmit the sampled digital word output from the network device.

4. The network device according to claim 1 , wherein the built-in accuracy test circuit is configured to provide the sampled digital word output to a controller in the network device.

5. The network device according to claim 1 , wherein the external reference signal used by the built-in accuracy test circuit to derive the timing of the sampling of the digital word output comprises a pulse-per-second (PPS) signal.

6. The network device according to claim 1 , wherein the accuracy of the hardware clock is indicated by a deviation between the sampled network time and the external reference signal.

7. The network device according to claim 1 , wherein the external reference signal comprises a dedicated test signal, which differs from a pulse-per-second (PPS) signal and which comprises a predefined pattern, and wherein the built-in accuracy test circuit is configured to identify the dedicated test signal and to sample the network time at the timing derived from the predefined pattern.

8. The network device according to claim 1 , wherein the external reference signal used by the built-in accuracy test circuit to derive the timing of the sampling of the digital word output comprises a 10 MHz signal.

9. The network device according to claim 1 , wherein the hardware clock is configured to indicate the network time on a parallel output interface, and wherein the built-in accuracy test circuit comprises a set of Flip-Flops (FFs) that are configured to sample the parallel output interface at the timing derived from the external reference signal.

10. A method, comprising:
in a network device, communicating packets over a communication network;
indicating a network time, used for synchronizing network devices in the communication network, using a hardware clock which outputs a digital word indicative of the network time in the network device; and
checking an accuracy of the hardware clock using a built-in accuracy test circuit in the network device, wherein the built-in accuracy test circuit receives an external reference signal having a predefined pattern of rising and/or falling edges, and samples the digital word, which is output by the hardware clock, at a timing that is derived from the external reference signal.

11. The method according to claim 10 , wherein indicating the network time comprises tracking the network time in accordance with a Precision Time Protocol (PTP).

12. The method according to claim 10 , wherein checking the accuracy of the hardware clock further comprises transmitting the sampled digital word output from the network device.

13. The method according to claim 10 , wherein checking the accuracy of the hardware clock further comprises providing the sampled digital word output to a controller in the network device.

14. The method according to claim 10 , wherein the external reference signal used by the built-in accuracy test circuit to derive the timing of the sampling of the digital word output comprises a pulse-per-second (PPS) signal.

15. The method according to claim 10 , wherein the accuracy of the hardware clock is indicated by a deviation between the sampled network time and the external reference signal.

16. The method according to claim 10 , wherein the external reference signal comprises a dedicated test signal, which differs from a pulse-per-second (PPS) signal and which comprises a predefined pattern, and wherein sampling the network time comprises identifying the dedicated test signal and sampling the network time at the timing derived from the predefined pattern.

17. The method according to claim 10 , wherein the external reference signal used by the built-in accuracy test circuit to derive the timing of the sampling of the digital word output comprises a 10 MHz signal.

18. The method according to claim 10 , wherein indicating the network time comprises outputting the network time on a parallel output interface, and wherein sampling the network time comprises sampling the parallel output interface at the timing derived from the external reference signal using a set of Flip-Flops (FFs).

19. The network device according to claim 1 , wherein the external reference signal tracks the actual network time with high accuracy.

20. The network device according to claim 5 , wherein the hardware clock is configured to discipline its timing using the PPS signal, which is also used by the built-in accuracy test circuit to derive the timing of the sampling of the digital word output.

21. The network device according to claim 5 , wherein the hardware clock is configured to discipline its timing using a discipline signal, different from the PPS signal used by the built-in accuracy test circuit to derive the timing of the sampling of the digital word output.

Assignees

• Mellanox Technologies Ltd

Inventors

• Mula Liron
• Levi Dotan David
• Almog Ariel

Classifications

• H04J3/14 Primary

  Monitoring arrangements {(for SDH/SONET rings H04J3/085)} · CPC title

• H04J3/0667 Primary

  Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays (arrangements for monitoring round trip delays in packet switching networks H04L43/0864) · CPC title

• H04L7/0012 Primary

  by comparing receiver clock with transmitter clock · CPC title

• H04J3/0697

  Synchronisation in a packet node · CPC title

• H04J3/0644

  External master-clock · CPC title