Analog to digital converter and a method for analog to digital conversion

Patent metadata

Field	Value
Publication number	US-11588492-B2
Application number	US-202217872055-A
Country	US
Kind code	B2
Filing date	Jul 25, 2022
Priority date	May 6, 2021
Publication date	Feb 21, 2023
Grant date	Feb 21, 2023

Abstract

An analog to digital converter (ADC) receives first and second analog input signals. A charge sampling demultiplexer includes multiple capacitors that sample the first and second analog input signals, and generates multiple input samples representative of charge stored on the capacitors. A plurality of sub-ADCs each include first and second charge-to-time converters, which receive from the charge sampling demultiplexer respective first and second input sample of the first and second analog input signals and output respective first and second pulse-width-modulated (PWM) signals responsively to the respective first and second input samples. Temporal processing circuitry processes the PWM signals to generate a digital value indicative of a temporal difference between the first and second PWM signals. Output reordering circuitry receives the digital value from each of the sub-ADCs and generates a digital output indicative of a difference between the first and second analog input signals.

First claim

We claim:

1. An analog to digital converter (ADC), comprising:
an input stage configured to receive first and second analog input signals;
a charge sampling demultiplexer, which comprises multiple capacitors that are coupled to sample the first and second analog input signals, and which is configured to generate multiple input samples representative of charge stored on the capacitors;
a plurality of sub-ADCs, each sub-ADC comprising:
first and second charge-to-time converters, which are coupled to receive from the charge sampling demultiplexer a respective first input sample of the first analog input signal and a respective second input sample of the second analog input signal and to output respective first and second pulse-width-modulated (PWM) signals responsively to the respective first and second input samples; and
temporal processing circuitry, which is coupled to process the PWM signals to generate a digital value indicative of a temporal difference between the first and second PWM signals; and

output reordering circuitry, which is coupled to receive the digital value from each of the sub-ADCs and to generate a digital output indicative of a difference between the first and second analog input signals.

2. The ADC according to claim 1 , wherein the temporal processing circuitry comprises multiple sampling latches, which are configured to detect a phase difference between the first and second PWM signals, and a digital processing block, which is configured to generate the digital value responsively to the phase difference.

3. The ADC according to claim 2 , and comprising a counter phase tracking circuit, which is configured to generate multiple phase-shifted clock signals that are phase shifted from one another other, wherein the sampling latches are configured to detect the phase difference using the multiple phase-shifted clock signals.

4. The ADC according to claim 3 , wherein the counter phase tracking circuit is further configured to generate multiple counter sampling signals, and wherein the multiple sampling latches comprise phase sampling latches, which are configured to detect a first phase difference value between the first and second PWM signals responsively to the phase-shifted clock signals, and counter sampling latches, which are configured to detect a second phase difference value between the first and second PWM signals responsively to the counter sampling signals, and
wherein the digital processing block is configured to generate the digital value responsively to the first and second phase difference values.

5. The ADC according to claim 4 , wherein the counter sampling latches are configured to output, responsively to the counter sampling signals, a first counter value indicative of a first edge of a first pulse in the first PWM signal and a second counter value indicative of a second edge of a second pulse in the second PWM signal.

6. The ADC according to claim 2 , wherein the digital processing block is configured to generate the digital value by applying a linear operation to the detected phase difference.

7. A method for analog to digital conversion, comprising:
receiving first and second analog input signals;
sampling the first and second analog input signals in a charge sampling demultiplexer, which comprises multiple capacitors that are coupled to sample the first and second analog input signals, and generates multiple input samples representative of charge stored on the capacitors;
digitizing the input samples to a plurality of sub-ADCs, each sub-ADC comprising:
first and second charge-to-time converters, which are coupled to receive from the charge sampling demultiplexer a respective first input sample of the first analog input signal and a respective second input sample of the second analog input signal and to output respective first and second pulse-width-modulated (PWM) signals responsively to the respective first and second input samples; and
temporal processing circuitry, which is coupled to process the PWM signals to generate a digital value indicative of a temporal difference between the first and second PWM signals; and

generating a digital output indicative of a difference between the first and second analog input signals using the digital value generated by each of the sub-ADCs.

8. The method according to claim 7 , wherein the temporal processing circuitry comprises multiple sampling latches, which detect a phase difference between the first and second PWM signals, and a digital processing block, which generates the digital value responsively to the phase difference.

9. The method according to claim 8 , and comprising generating multiple phase-shifted clock signals that are phase shifted from one another other, wherein the sampling latches detect the phase difference using the multiple phase-shifted clock signals.

10. The method according to claim 9 , and comprising generating multiple counter sampling signals, wherein the multiple sampling latches comprise phase sampling latches, which detect a first phase difference value between the first and second PWM signals responsively to the phase- shifted clock signals, and counter sampling latches, which detect a second phase difference value between the first and second PWM signals responsively to the counter sampling signals, and
wherein the digital processing block generates the digital value responsively to the first and second phase difference values.

11. The method according to claim 10 , wherein the counter sampling latches output, responsively to the counter sampling signals, a first counter value indicative of a first edge of a first pulse in the first PWM signal and a second counter value indicative of a second edge of a second pulse in the second PWM signal.

12. The method according to claim 8 , wherein the digital processing block generates the digital value by applying a linear operation to the detected phase difference.

Assignees

• Apple Inc

Inventors

• Levi Andrei
• Galambos Tiberiu Carol

Classifications

• H03M1/0617 Primary

  characterised by the use of methods or means not specific to a particular type of detrimental influence · CPC title

• H03M1/64

  with intermediate conversion to phase of sinusoidal {or similar periodical} signals · CPC title

• H03M1/1009

  Calibration · CPC title