Signal generation circuit and method, and digit-to-time conversion circuit and method

Patent metadata

Field	Value
Publication number	US-11588491-B2
Application number	US-202017296305-A
Country	US
Kind code	B2
Filing date	Aug 10, 2020
Priority date	Aug 30, 2019
Publication date	Feb 21, 2023
Grant date	Feb 21, 2023

Abstract

A signal generating electric circuit, a signal generating method, a digit-to-time converting electric circuit and a digit-to-time converting method. The signal generating electric circuit includes: a first generating electric circuit configured for, based on a first frequency control word and a reference time unit, generating a periodic first output signal; and a second generating electric circuit configured for, based on a second frequency control word and the reference time unit, generating a periodic second output signal. The first frequency control word includes a first integer part and a first fractional part, the second frequency control word includes a second integer part and a second fractional part, the first integer part is equal to the second integer part, the first fractional part is not zero, the second fractional part is zero, and a period of the first output signal and a period of the second output signal are not equal.

First claim

The invention claimed is:

1. A signal generating electric circuit, comprising:
a first generating electric circuit configured for, based on a first frequency control word and a reference time unit, generating a periodic first output signal; and
a second generating electric circuit configured for, based on a second frequency control word and the reference time unit, generating a periodic second output signal;
wherein the first frequency control word comprises a first integer part and a first fractional part, the second frequency control word comprises a second integer part and a second fractional part, the first integer part is equal to the second integer part, the first fractional part is not zero, the second fractional part is zero, and a period of the first output signal and a period of the second output signal are not equal;
wherein the first generating electric circuit comprises a first digitally controlled oscillator sub-circuit and a first converting sub-circuit, the first digitally controlled oscillator sub-circuit is configured for, based on the first frequency control word and the reference time unit, generating a first intermediate signal, and the first converting sub-circuit is configured for converting the first intermediate signal into the first output signal;
the second generating electric circuit comprises a second digitally controlled oscillator sub-circuit, and the second digitally controlled oscillator sub-circuit is configured for, based on the second frequency control word and the reference time unit, generating the second output signal;
the first intermediate signal is generated by interlacing between a pulse having a first primitive period and a pulse having a second primitive period, and an average period of the first intermediate signal is expressed by using the following formula:
T h =(1− r h )· T A +r h ·T B ,

wherein T h represents the average period of the first intermediate signal, r h represents the first fractional part, T A represents the first primitive period, and T B represents the second primitive period; and
the period of the second output signal is expressed by using the following formula:
T I =T A ,

wherein T I represents the period of the second output signal.

2. The signal generating electric circuit according to claim 1 , wherein a periodic inequality between the period of the first output signal and the period of the second output signal is related to the reference time unit and the first fractional part.

3. The signal generating electric circuit according to claim 1 , wherein the first converting sub-circuit is configured for filtering out a high-frequency component of the first intermediate signal to obtain the first output signal.

4. The signal generating electric circuit according to claim 1 , wherein the first converting sub-circuit comprises a second phase detector, a second loop filter, a second voltage-controlled oscillator and a second frequency divider;
the second voltage-controlled oscillator is configured for, according to a control variable, generating an oscillating signal having a second preset oscillation frequency;
the second frequency divider is configured for performing frequency division to the oscillating signal to obtain a frequency-divided signal;
the second phase detector is configured for comparing to obtain a difference between a frequency of the first intermediate signal and a frequency of the frequency-divided signal, to output a difference variable;
the second loop filter is configured for filtering out a high-frequency component of the difference variable, to generate the control variable controlling the second voltage-controlled oscillator; and
the second voltage-controlled oscillator is further configured for, when the frequency of the first intermediate signal and the frequency of the frequency-divided signal are equal, generating and outputting the first output signal.

5. The signal generating electric circuit according to claim 4 , wherein parameters of the second loop filter are determined according to the frequency of the first intermediate signal and a least significant bit of the first fractional part.

6. The signal generating electric circuit according to claim 5 , wherein the parameters of the second loop filter include a bandwidth of the second loop filter, and the bandwidth of the second loop filter is determined according to the following formula:
Bwlp≤ f h ·r LSB ,

wherein Bwlp represents the bandwidth of the second loop filter, f h represents a mean frequency of the first intermediate signal, and r LSB represents a value corresponding to the least significant bit of the first fractional part.

7. The signal generating electric circuit according to claim 1 , wherein the first digitally controlled oscillator sub-circuit and the second digitally controlled oscillator sub-circuit comprise a time-average-frequency direct-period synthesizer.

8. The signal generating electric circuit according to claim 1 , wherein the signal generating electric circuit further comprises a reference-time-unit generating electric circuit, and the reference-time-unit generating electric circuit is configured for generating the reference time unit.

9. The signal generating electric circuit according to claim 8 , wherein the reference-time-unit generating electric circuit comprises:
a first voltage-controlled oscillator configured for oscillating with a first preset oscillation frequency;
a phase-locked-loop circuit configured for locking an output frequency of the first voltage-controlled oscillator as a reference output frequency; and
K output terminals configured for outputting K output signals whose phases are evenly separated, wherein K is a positive integer greater than 1;
wherein the reference output frequency is expressed as f Δ , the reference time unit is a time span between any two neighboring output signals outputted by the K output terminals, the reference time unit is expressed as Δ, and Δ=1/(K·f Δ ).

10. The signal generating electric circuit according to claim 1 , further comprising: a control circuit;
wherein the control circuit is configured for determining the first frequency control word and the second frequency control word, outputting the first frequency control word to the first generating electric circuit, and outputting the second frequency control word to the second generating electric circuit.

11. A digit-to-time converting electric circuit, comprising:
the signal generating electric circuit according to claim 1 ; and
a time generating electric circuit configured for receiving a digital signal, the first output signal and the second output signal; and based on the digital signal, the first output signal and the second output signal, generating a first time-pulse signal or a second time-pulse signal corresponding to the digital signal;
wherein a first minimum time interval between a rising edge and a falling edge of the first time-pulse signal is related to the reference time unit and the first fractional part; or, the second time-pulse signal comprises a first sub-pulse signal and a second sub-pulse signal, and a second minimum time interval between a rising edge of the first sub-pulse signal and a rising edge of the second sub-pulse signal is related to the reference time unit and the first fractional part.

12. The digit-to-time converting electric circuit according to claim 11 , further comprising a phase-detector circuit;
wherein the phase-detector circuit is configured for determining a phase relation between the first output signal and the second output signal, to generate an indicator signal indicating that a phas

Assignees

• Beijing Boe Technology Dev Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Wei Xiangye
• Xiu Liming

Classifications

• H03L7/099

  concerning mainly the controlled oscillator of the loop · CPC title

• H03L7/197

  a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division {(H03L7/1806 takes precedence)} · CPC title

• H03L7/0992 Primary

  comprising a counter or a frequency divider · CPC title

• H03L7/22

  using more than one loop · CPC title

• H03L7/1974 Primary

  for fractional frequency division · CPC title