Low powered clock driving

Patent metadata

Field	Value
Publication number	US-11588474-B2
Application number	US-202117347760-A
Country	US
Kind code	B2
Filing date	Jun 15, 2021
Priority date	Jun 15, 2021
Publication date	Feb 21, 2023
Grant date	Feb 21, 2023

Abstract

A clock driver circuit for low powered clock driving may include: a multiple phase divider; a buffer supplying at least one of multiple phases to the multiple phase divider at a center frequency that is an integer multiple of an input frequency; and wherein the multiple phase divider and the buffer share a same current from a supply rail.

First claim

What is claimed is:

1. A clock driver circuit for low powered clock driving, comprising:
a multiple phase divider;
a buffer supplying at least one of multiple phases to the multiple phase divider at a center frequency that is an integer multiple of an input frequency; and
wherein the multiple phase divider and the buffer share a same current from a supply rail.

2. The clock driver circuit of claim 1 , further comprising an operational amplifier coupled to the buffer.

3. The clock driver circuit of claim 1 , wherein the multiple phase divider and the buffer are stacked.

4. The clock driver circuit of claim 1 , further comprising a clock signal generator coupled to the multiple phase divider.

5. The clock driver circuit of claim 4 , wherein two or more of the clock signal generator, the multiple phase divider and the buffer are stacked.

6. The clock driver circuit of claim 1 , further comprising a power down switch for the buffer.

7. The clock driver circuit of claim 6 , wherein the power down switch is connected between a main voltage supply and an intermediate voltage supply.

8. The clock driver circuit of claim 1 , wherein one or more outputs from the multiple phase divider are directly coupled to one or more inputs of the buffer.

9. The clock driver circuit of claim 1 , wherein the buffer is configured to resonate at a frequency that is an integer multiple of an output frequency of the multiple phase divider.

10. The clock driver circuit of claim 9 , wherein an output frequency of the clock driver circuit is calculated as F out =(M/N)*F in , where F in is the input frequency, N is an integer frequency division provided by the multiple phase divider and M is a frequency multiplier obtained by resonating at an output of the buffer amplifying the Mth harmonic of a signal at an output of the multiple phase divider.

11. An apparatus for low powered clock driving, comprising:
a clock driver circuit comprising:
a multiple phase divider;
a buffer; and
wherein the multiple phase divider and the buffer share a same current from a supply rail.

12. The apparatus of claim 11 , further comprising an operational amplifier coupled to the buffer.

13. The apparatus of claim 11 , wherein the multiple phase divider and the buffer are stacked.

14. The apparatus of claim 11 , wherein the clock driver circuit further comprises an oscillator coupled to the multiple phase divider.

15. The apparatus of claim 14 , wherein two or more of the oscillator, the multiple phase divider and the buffer are stacked.

16. The apparatus of claim 14 , wherein the clock driver circuit further comprises a power down switch for the buffer connected between a main voltage supply and an intermediate voltage supply.

17. The apparatus of claim 11 , wherein one or more outputs from the multiple phase divider are directly coupled to one or more inputs of the buffer.

18. A method for low powered clock driving, comprising:
receiving, by a clock driver circuit comprising a multiple phase divider and a buffer sharing a same current, a clock signal; and
outputting, by the clock driver circuit, a divided clock signal driven by the clock driver circuit.

19. The method of claim 18 , wherein the multiple phase divider and the buffer are stacked.

20. The method of claim 18 , wherein the divided clock signal driven by the clock driver circuit is output to a plurality of array elements.

Assignees

• IBM

Inventors

• Ramirez Daniel
• Chakraborty Sudipto

Classifications

• H03K3/353 Primary

  by the use, as active elements, of field-effect transistors with internal or external positive feedback (H03K3/023, H03K3/027 take precedence) · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• H03K2005/00195

  using FET's · CPC title

• H03K5/13 Primary

  Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals · CPC title